OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 9
OM13013,598
Manufacturer Part Number
OM13013,598
Description
BOARD DEMO IAR LPC1227 JLINKLITE
Manufacturer
NXP Semiconductors
Series
-r
Specifications of OM13013,598
Design Resources
LPC122x-SK Brd Schematic
Processor To Be Evaluated
LPC1227
Processor Series
LPC122x
Data Bus Width
32 bit
Interface Type
UART, SSP, SPI, I2C
Cpu Core
ARM Cortex-M0
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Operating Supply Voltage
3 V to 3.6 V
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-6885
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3.1 How to read this chapter
3.2 Features
3.3 Description
3.4 Interrupt sources
UM10441
User manual
The NVIC is part of the ARM Cortex-M0 system block is identical on all LPC122x parts.
The Nested Vectored Interrupt Controller (NVIC) is an integral part of the Cortex-M0. The
tight coupling to the CPU allows for low interrupt latency and efficient processing of late
arriving interrupts.
The source of the NMI is configurable (see
can be selected for the NMI functionality.
Refer to the ARM Cortex-M0 Technical Reference Manual and to the ARM Cortex-M0
appendix
Table 4
may have one or more interrupt lines to the Vectored Interrupt Controller. Each line may
represent more than one interrupt source. There is no significance or priority about what
line is connected where, except for certain standards from ARM.
Table 4.
Exception
Number
11 to 0
12
13
•
•
•
•
•
•
•
UM10441
Chapter 3: LPC122x Nested Vectored Interrupt Controller
(NVIC)
Rev. 1 — 15 February 2011
Nested Vectored Interrupt Controller that is an integral part of the ARM Cortex-M0.
Tightly coupled interrupt controller provides low interrupt latency.
Controls system exceptions and peripheral interrupts.
Supports 32 vectored interrupts.
Four programmable interrupt priority levels with hardware priority level masking.
Software interrupt generation.
Non-Maskable Interrupt (NMI) with configurable source.
lists the interrupt sources for each peripheral function. Each peripheral device
(Section
Connection of interrupt sources to the Vectored Interrupt Controller
Function
start logic wake-up
interrupts
I
CT16B0
2
C
All information provided in this document is subject to legal disclaimers.
25.5.2) for details of NVIC operation and the register description.
Rev. 1 — 15 February 2011
Flag(s)
Each interrupt is connected to a PIO input pin serving as
wake-up pin when the part is in Deep-sleep mode; Interrupt 0
to 11 correspond to PIO0_0 to PIO0_11(see
SI (state change)
Match 3 to 0
Capture 3 to 0
Section
4.5.29). Multiple peripheral interrupts
© NXP B.V. 2011. All rights reserved.
Table
User manual
37).
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