OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 280

• Manufacturer Part Number: OM13013,598
• Description: BOARD DEMO IAR LPC1227 JLINKLITE
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of OM13013,598

• Design Resources: LPC122x-SK Brd Schematic
• Processor To Be Evaluated: LPC1227
• Processor Series: LPC122x
• Data Bus Width: 32 bit
• Interface Type: UART, SSP, SPI, I2C
• Cpu Core: ARM Cortex-M0
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3 V to 3.6 V
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6885

NXP Semiconductors
17.6 Watchdog lock features
17.7 Register description
UM10441
User manual
The watchdog oscillator can be powered down in the PDRUNCFG register
(Section
clock to the watchdog register block (PCLK) can be disabled in the AHBCLKCTRL
register
The watchdog timer operation can be locked in several ways to ensure that the WDT is
always running. The lock features are enabled by a one-time write to the corresponding
lock register bit and can only be reversed by a chip reset.
The following lock mechanisms can be applied:
Remark: The lock features must be used with caution.
Table 263. Register overview: Watchdog timer (base address 0x4000 4000)
Name
MOD
TC
FEED
TV
•
•
•
•
•
•
•
Lock the enable/disable state of the WDT and simultaneously whether the watchdog
triggers an interrupt or a reset
Lock the switching of clock sources. This lock mechanism prevents changing to a
clock source that is powered down
Lock the power control to any WDT clock source in the PDRUNCFG, PDSLEEPCFG,
PDAWAKECFG registers
Lock updating the WDT reload value
Lock entering Deep power-down mode
configuration registers PDSLEEPCFG, PDRUNCFG, and PDAWAKECFG before
locking power control and the clock source select.
The watchdog oscillator must be turned on before locking power control if the WDT is
used in Deep-sleep mode.
Ensure that the WDT clock source is selected to be powered on in all three power
(Table
4.5.40) if it is not used - unless bit 5 in the MOD register is set
21) for power savings.
Access Address
R/W
R/W
WO
RO
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 15 February 2011
offset
0x000
0x004
0x008
0x00C
Chapter 17: LPC122x Windowed Watchdog Timer (WWDT)
(Table
Description
Watchdog mode register. This register
contains the basic mode and status of the
Watchdog Timer.
Watchdog timer constant register. This register
determines the time-out value.
Watchdog feed sequence register. Writing
0xAA followed by 0x55 to this register reloads
the Watchdog timer with the value contained in
TC.
Watchdog timer value register. This register
reads out the current value of the Watchdog
timer.
(Table
264).
(Table
264).
(Table
(Table
269).
264).
264).
UM10441
© NXP B.V. 2011. All rights reserved.
(Table
Reset
value
0x0000
0003
0x0000
FFFF
NA
0xFF
264). The
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