OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 231
OM13013,598
Manufacturer Part Number
OM13013,598
Description
BOARD DEMO IAR LPC1227 JLINKLITE
Manufacturer
NXP Semiconductors
Series
-r
Specifications of OM13013,598
Design Resources
LPC122x-SK Brd Schematic
Processor To Be Evaluated
LPC1227
Processor Series
LPC122x
Data Bus Width
32 bit
Interface Type
UART, SSP, SPI, I2C
Cpu Core
ARM Cortex-M0
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Operating Supply Voltage
3 V to 3.6 V
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-6885
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UM10441
User manual
Fig 29. Texas Instruments Synchronous Serial Frame Format: a) Single and b) Continuous/back-to-back Two
a. Single frame transfer
b. Continuous/back-to-back frames transfer
Frames Transfer
DX/DR
12.7.2.1 Clock Polarity (CPOL) and Phase (CPHA) control
CLK
12.7.2 SPI frame format
FS
For device configured as a master in this mode, CLK and FS are forced LOW, and the
transmit data line DX is in 3-state mode whenever the SSP is idle. Once the bottom entry
of the transmit FIFO contains data, FS is pulsed HIGH for one CLK period. The value to
be transmitted is also transferred from the transmit FIFO to the serial shift register of the
transmit logic. On the next rising edge of CLK, the MSB of the 4-bit to 16-bit data frame is
shifted out on the DX pin. Likewise, the MSB of the received data is shifted onto the DR
pin by the off-chip serial slave device.
Both the SSP and the off-chip serial slave device then clock each data bit into their serial
shifter on the falling edge of each CLK. The received data is transferred from the serial
shifter to the receive FIFO on the first rising edge of CLK after the LSB has been latched.
The SPI interface is a four-wire interface where the SSEL signal behaves as a slave
select. The main feature of the SPI format is that the inactive state and phase of the SCK
signal are programmable through the CPOL and CPHA bits within the SSPCR0 control
register.
When the CPOL clock polarity control bit is LOW, it produces a steady state low value on
the SCK pin. If the CPOL clock polarity control bit is HIGH, a steady state high value is
placed on the CLK pin when data is not being transferred.
DX/DR
CLK
FS
MSB
All information provided in this document is subject to legal disclaimers.
4 to 16 bit
Rev. 1 — 15 February 2011
MSB
LSB
4 to 16 bit
MSB
LSB
Chapter 12: LPC122x SSP controller
4 to 16 bit
LSB
UM10441
© NXP B.V. 2011. All rights reserved.
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