OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 45
OM13013,598
Manufacturer Part Number
OM13013,598
Description
BOARD DEMO IAR LPC1227 JLINKLITE
Manufacturer
NXP Semiconductors
Series
-r
Specifications of OM13013,598
Design Resources
LPC122x-SK Brd Schematic
Processor To Be Evaluated
LPC1227
Processor Series
LPC122x
Data Bus Width
32 bit
Interface Type
UART, SSP, SPI, I2C
Cpu Core
ARM Cortex-M0
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Operating Supply Voltage
3 V to 3.6 V
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-6885
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UM10441
User manual
4.5.41 Device ID register
4.5.42 Flash configuration register
Table 50.
This device ID register is a read-only register and contains the device ID for each
LPC122x part. This register is also read by the ISP/IAP commands (see
and
Table 51.
Depending on the system clock frequency, access to the flash memory can be configured
with various access times by writing to the FLASHCFG register at address 0x5006 0028.
Remark: Settings in this register only have an effect when the FLASH_OVERRIDE bit in
the PRESET_CTRL register (see
Table 52.
Bit
15
31:16
Bit
31:0
Bit
1:0
31:2
Section
Symbol
RDCFG
-
Symbol
COMP_PD
-
Symbol
DEVICEID
description
Device ID register (DEVICE_ID, address 0x4004 83F4) bit description
Flash configuration register (FLASHCFG, address 0x5006 0028) bit description
Power-down configuration register (PDRUNCFG, address 0x4004 8238) bit
20.8.5).
All information provided in this document is subject to legal disclaimers.
Value Description
0x0
0x1
0x2
0x3
Rev. 1 — 15 February 2011
…continued
Description
Device ID for LPC122x parts:
LPC1227FBD64/301 = 0x3670 002B
LPC1227FBD48/301 = 0x3670 002B
LPC1226FBD64/301 = 0x3660 002B
LPC1226FBD48/301 = 0x3660 002B
LPC1225FBD64/321 = 0x3652 002B
LPC1225FBD64/301 = 0x3650 002B
LPC1225FBD48/321 = 0x3652 002B
LPC1225FBD48/301 = 0x3650 002B
LPC1224FBD64/121 = 0x3642 C02B
LPC1224FBD64/101 = 0x3640 C02B
LPC1224FBD48/121 = 0x3642 C02B
LPC1224FBD48/101 = 0x3640 C02B
Flash memory read access time:
2 system clock cycles flash access time
3 system clock cycles flash access time
4 system clock cycles flash access time
5 system clock cycles flash access time
Reserved.
Value
0
1
-
Description
Comparator power-down
Powered
Powered down
Reserved
Table
Chapter 4: LPC122x System control (SYSCON)
9) is set to 0 allowing multi-cycle read access.
UM10441
© NXP B.V. 2011. All rights reserved.
Reset value
part-dependent
Reset value
0
-
Section 20.7.11
45 of 442
Reset
value
1
0
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