OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 237

• Manufacturer Part Number: OM13013,598
• Description: BOARD DEMO IAR LPC1227 JLINKLITE
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of OM13013,598

• Design Resources: LPC122x-SK Brd Schematic
• Processor To Be Evaluated: LPC1227
• Processor Series: LPC122x
• Data Bus Width: 32 bit
• Interface Type: UART, SSP, SPI, I2C
• Cpu Core: ARM Cortex-M0
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3 V to 3.6 V
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6885

NXP Semiconductors
UM10441
User manual
12.7.3.1 Setup and hold time requirements on CS with respect to SK in Microwire
mode
In the Microwire mode, the SSP slave samples the first bit of receive data on the rising
edge of SK after CS has gone LOW. Masters that drive a free-running SK must ensure
that the CS signal has sufficient setup and hold margins with respect to the rising edge of
SK.
Figure 36
edge on which the first bit of receive data is to be sampled by the SSP slave, CS must
have a setup of at least two times the period of SK on which the SSP operates. With
respect to the SK rising edge previous to this edge, CS must have a hold of at least one
SK period.
Fig 35. Microwire frame format (continuos transfers)
Fig 36. Microwire frame format setup and hold details
CS
SO
SK
SI
illustrates these setup and hold time requirements. With respect to the SK rising
All information provided in this document is subject to legal disclaimers.
LSB
CS
SK
SI
0
Rev. 1 — 15 February 2011
MSB
output data
4 to 16 bit
LSB
MSB
t
HOLD
= t
8 bit control
SK
t
SETUP
Chapter 12: LPC122x SSP controller
=2*t
SK
LSB
MSB
output data
4 to 16 bit
UM10441
© NXP B.V. 2011. All rights reserved.
LSB
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