OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 134

• Manufacturer Part Number: OM13013,598
• Description: BOARD DEMO IAR LPC1227 JLINKLITE
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of OM13013,598

• Design Resources: LPC122x-SK Brd Schematic
• Processor To Be Evaluated: LPC1227
• Processor Series: LPC122x
• Data Bus Width: 32 bit
• Interface Type: UART, SSP, SPI, I2C
• Cpu Core: ARM Cortex-M0
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3 V to 3.6 V
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6885

NXP Semiconductors
UM10441
User manual
8.3.10 GPIO interrupt event register
8.3.11 GPIO interrupt mask register
8.3.7 GPIO data direction register
8.3.8 GPIO interrupt sense register
8.3.9 GPIO interrupt both edges sense register
Table 128. GPIO data direction register (DIR - address 0x5000 0020 (GPIO0), 0x5001 0020
Table 129. GPIO interrupt sense register (IS - address 0x5000 0024 (GPIO0), 0x5001 0024
Table 130. GPIO interrupt both edges sense register (IBE - address 0x5000 0028 (GPIO0),
Table 131. GPIO interrupt event register (IEV - address 0x5000 002C (GPIO0), 0x5001 002C
Bits set to HIGH in the IE register allow the corresponding pins to trigger their individual
interrupts and the combined INTR line. Clearing a bit disables interrupt triggering on that
pin.
Bit
31:0
Bit
31:0
Bit
31:0
Bit
31:0
Symbol
IO
Symbol
ISENSE
Symbol Description
IBE
Symbol
IEV
(GPIO1), 0x5002 0020 (GPIO2)) bit description
(GPIO1), 0x5002 0024 (GPIO2)) bit description
0x5001 0028 (GPIO1), 0x5002 0028 (GPIO2)) bit description
(GPIO1), 0x5002 002C (GPIO2)) bit description
All information provided in this document is subject to legal disclaimers.
Selects interrupt on pin PIOn_x to be triggered on both
edges.
0 = Interrupt on pin PIOn_x is controlled through register IEV.
1 = Both edges on pin PIOn_x trigger an interrupt.
Description
0 = Pin PIOn_x is configured as input.
1 = Pin PIOn_x is configured as output.
Description
0 = Interrupt on pin PIOn_x is configured as edge sensitive.
1 = Interrupt on pin PIOn_x is configured as level sensitive.
Description
falling edges.
0 = Depending on setting in register IS, falling edges or
LOW level on pin PIOn_x trigger an interrupt.
1 = Depending on setting in register IS, rising edges or
HIGH level on pin PIOn_x trigger an interrupt.
Selects GPIO pin PIOn_x as input or output.
Selects interrupt on pin PIOn_x as level or edge sensitive.
Selects interrupt on pin PIOn_x to be triggered rising or
Rev. 1 — 15 February 2011
Chapter 8: LPC122x General Purpose I/O (GPIO)
UM10441
© NXP B.V. 2011. All rights reserved.
Reset
value
0x00
Reset
value
0x00
Reset
value
0x00
Reset
value
0x00
Access
R/W
Access
R/W
Access
R/W
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Access
R/W