OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 367

• Manufacturer Part Number: OM13013,598
• Description: BOARD DEMO IAR LPC1227 JLINKLITE
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of OM13013,598

• Design Resources: LPC122x-SK Brd Schematic
• Processor To Be Evaluated: LPC1227
• Processor Series: LPC122x
• Data Bus Width: 32 bit
• Interface Type: UART, SSP, SPI, I2C
• Cpu Core: ARM Cortex-M0
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3 V to 3.6 V
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6885

NXP Semiconductors
UM10441
User manual
25.3.2.4 Software ordering of memory accesses
Table 360. Memory access behavior
[1]
The Code, SRAM, and external RAM regions can hold programs.
The order of instructions in the program flow does not always guarantee the order of the
corresponding memory transactions. This is because:
Section 25–25.3.2.2
of memory accesses. Otherwise, if the order of memory accesses is critical, software
must include memory barrier instructions to force that ordering. The processor provides
the following memory barrier instructions:
DMB — The Data Memory Barrier (DMB) instruction ensures that outstanding memory
transactions complete before subsequent memory transactions. See
DSB — The Data Synchronization Barrier (DSB) instruction ensures that outstanding
memory transactions complete before subsequent instructions execute. See
Section
ISB — The Instruction Synchronization Barrier (ISB) ensures that the effect of all
completed memory transactions is recognizable by subsequent instructions. See
Section
The following are examples of using memory barrier instructions:
Address
range
0x00000000-
0x1FFFFFFF
0x20000000-
0x3FFFFFFF
0x40000000-
0x5FFFFFFF
0x60000000-
0x9FFFFFFF
0xA0000000-
0xDFFFFFFF
0xE0000000-
0xE00FFFFF
0xE0100000-
0xFFFFFFFF
•
•
•
See
the processor can reorder some memory accesses to improve efficiency, providing
this does not affect the behavior of the instruction sequence
memory or devices in the memory map might have different wait states
some memory accesses are buffered or speculative.
Section 25–25.3.2.1
25–25.4.7.4.
25–25.4.7.5.
Memory
region
Code
SRAM
Peripheral
External
RAM
External
device
Private Peripheral
Bus
Device
All information provided in this document is subject to legal disclaimers.
describes the cases where the memory system guarantees the order
Rev. 1 — 15 February 2011
for more information.
Memory
type
Normal
Normal
Device
Normal
Device
Strongly-ordered
Device
[1]
Chapter 25: LPC122x Appendix ARM Cortex-M0
XN
-
-
XN
-
XN
XN
XN
[1]
Description
code. You can also put data here.
can also put code here.
External device memory.
External device memory.
System timer, and System Control
Block. Only word accesses can be
used in this region.
Vendor specific.
Executable region for program
Executable region for data. You
Executable region for data.
This region includes the NVIC,
Section
UM10441
© NXP B.V. 2011. All rights reserved.
25–25.4.7.3.
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