OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 358

• Manufacturer Part Number: OM13013,598
• Description: BOARD DEMO IAR LPC1227 JLINKLITE
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of OM13013,598

• Design Resources: LPC122x-SK Brd Schematic
• Processor To Be Evaluated: LPC1227
• Processor Series: LPC122x
• Data Bus Width: 32 bit
• Interface Type: UART, SSP, SPI, I2C
• Cpu Core: ARM Cortex-M0
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3 V to 3.6 V
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6885

NXP Semiconductors
25.3 Processor
UM10441
User manual
25.3.1.1 Processor modes
25.3.1.2 Stacks
25.3.1.3 Core registers
25.3.1 Programmers model
System timer — The system timer, SysTick, is a 24-bit count-down timer. Use this as a
Real Time Operating System (RTOS) tick timer or as a simple counter.
This section describes the Cortex-M0 programmers model. In addition to the individual
core register descriptions, it contains information about the processor modes and stacks.
The processor modes are:
Thread mode — Used to execute application software. The processor enters Thread
mode when it comes out of reset.
Handler mode — Used to handle exceptions. The processor returns to Thread mode
when it has finished all exception processing.
The processor uses a full descending stack. This means the stack pointer indicates the
last stacked item on the stack memory. When the processor pushes a new item onto the
stack, it decrements the stack pointer and then writes the item to the new memory
location. The processor implements two stacks, the main stack and the process stack,
with independent copies of the stack pointer, see
In Thread mode, the CONTROL register controls whether the processor uses the main
stack or the process stack, see
always uses the main stack. The options for processor operations are:
Table 352. Summary of processor mode and stack use options
The processor core registers are:
Processor
mode
Thread
Handler
All information provided in this document is subject to legal disclaimers.
Used to
execute
Applications
Exception
handlers
Rev. 1 — 15 February 2011
Section
Stack used
Main stack or process stack
See
Main stack
Chapter 25: LPC122x Appendix ARM Cortex-M0
25–25.3.1.3.7. In Handler mode, the processor
Section 25–25.3.1.3.7
Section
25.3.1.3.2.
UM10441
© NXP B.V. 2011. All rights reserved.
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