OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 230

• Manufacturer Part Number: OM13013,598
• Description: BOARD DEMO IAR LPC1227 JLINKLITE
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of OM13013,598

• Design Resources: LPC122x-SK Brd Schematic
• Processor To Be Evaluated: LPC1227
• Processor Series: LPC122x
• Data Bus Width: 32 bit
• Interface Type: UART, SSP, SPI, I2C
• Cpu Core: ARM Cortex-M0
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3 V to 3.6 V
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6885

NXP Semiconductors
12.7 Functional description
UM10441
User manual
12.6.10 SSP DMA Control Register
12.7.1 Texas Instruments synchronous serial frame format
Table 214. SSP interrupt Clear Register (ICR - address 0x4004 0020) bit description
The DMACR register is the DMA control register. It is a read/write register.
Table 215. SSP DMA Control Register (DMACR - address 0x4004 0024) bit description
Figure 29
by the SSP module.
Bit
0
1
31:2
Bit
0
1
31:2
Symbol
RXDMAE
TXDMAE
-
Symbol
RORIC
RTIC
-
shows the 4-wire Texas Instruments synchronous serial frame format supported
All information provided in this document is subject to legal disclaimers.
Description
Writing a 1 to this bit clears the “frame was received when
RxFIFO was full” interrupt.
Writing a 1 to this bit clears the “Rx FIFO was not empty and
has not been read for a time-out period” interrupt. The time-out
period is the same for master and slave modes and is
determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR
× [SCR+1]).
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
Value
0
1
0
1
Rev. 1 — 15 February 2011
Description
Receive DMA Enable
Receive DMA disabled.
DMA for the receive FIFO is enabled.
Transmit DMA Enable
Transmit DMA disabled.
DMA for the transmit FIFO is enabled.
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
Chapter 12: LPC122x SSP controller
UM10441
© NXP B.V. 2011. All rights reserved.
Reset value
NA
NA
NA
230 of 442
Reset
value
0
0
NA