OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 21

• Manufacturer Part Number: OM13013,598
• Description: BOARD DEMO IAR LPC1227 JLINKLITE
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of OM13013,598

• Design Resources: LPC122x-SK Brd Schematic
• Processor To Be Evaluated: LPC1227
• Processor Series: LPC122x
• Data Bus Width: 32 bit
• Interface Type: UART, SSP, SPI, I2C
• Cpu Core: ARM Cortex-M0
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3 V to 3.6 V
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6885

NXP Semiconductors
UM10441
User manual
4.5.12 Main clock source update enable register
4.5.13 System AHB clock divider register
4.5.11 Main clock source select register
Table 17.
This register selects the main system clock which can be either any input to the system
PLL, the output from the system PLL (sys_pllclkout), or the watchdog or IRC oscillators
directly. The main system clock clocks the core, the peripherals, and the memories.
The MAINCLKUEN register (see
the update to take effect.
Remark: When switching clock sources, both clocks must be running before updating the
clock source.
Table 18.
This register updates the clock source of the main clock with the new input clock after the
MAINCLKSEL register has been written to. In order for the update to take effect, first write
a zero to the MAINCLKUEN register and then write a one to MAINCLKUEN.
Table 19.
This register divides the main clock to provide the system clock to the core, memories,
and the peripherals. The system clock can be shut down completely by setting the DIV
bits to 0x0.
Bit
0
31:1
Bit
1:0
31:2
Bit
0
31:1
Symbol
ENA
-
Symbol
SEL
-
Symbol
ENA
-
0x4004 8044) bit description
Main clock source select register (MAINCLKSEL, address 0x4004 8070) bit
description
Main clock source update enable register (MAINCLKUEN, address 0x4004 8074)
bit description
System PLL clock source update enable register (SYSPLLCLKUEN, address
All information provided in this document is subject to legal disclaimers.
Value
0x0
0x1
0x2
0x3
-
Value
0
1
-
Value
0
1
-
Rev. 1 — 15 February 2011
Description
Clock source for main clock
IRC oscillator
Input clock to system PLL
WDT oscillator
System PLL clock out
Reserved
Description
Enable system PLL clock source update
No change
Update clock source
Reserved
Description
Enable main clock source update
No change
Update clock source
Reserved
Section
Chapter 4: LPC122x System control (SYSCON)
4.5.12) must be toggled from LOW to HIGH for
UM10441
© NXP B.V. 2011. All rights reserved.
Reset value
00
0x00
Reset value
0
0x00
Reset value
0x0
0x00
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