OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 166

• Manufacturer Part Number: OM13013,598
• Description: BOARD DEMO IAR LPC1227 JLINKLITE
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of OM13013,598

• Design Resources: LPC122x-SK Brd Schematic
• Processor To Be Evaluated: LPC1227
• Processor Series: LPC122x
• Data Bus Width: 32 bit
• Interface Type: UART, SSP, SPI, I2C
• Cpu Core: ARM Cortex-M0
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3 V to 3.6 V
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6885

NXP Semiconductors
UM10441
User manual
10.5.6 UART FIFO Control Register
[3]
[4]
The UART THRE interrupt (IIR[3:1] = 001) is a third level interrupt and is activated when
the UART THR FIFO is empty provided certain initialization conditions have been met.
These initialization conditions are intended to give the UART THR FIFO a chance to fill up
with data to eliminate many THRE interrupts from occurring at system start-up. The
initialization conditions implement a one character delay minus the stop bit whenever
THRE = 1 and there have not been at least two characters in the THR at one time since
the last THRE = 1 event. This delay is provided to give the CPU time to write data to THR
without a THRE interrupt to decode and service. A THRE interrupt is set immediately if the
UART THR FIFO has held two or more characters at one time and currently, the THR is
empty. The THRE interrupt is reset when a THR write occurs or a read of the IIR occurs
and the THRE is the highest interrupt (IIR[3:1] = 001).
The FCR controls the operation of the UART RX and TX FIFOs.
Table 169. UART FIFO Control Register (FCR - address 0x4000 C008, Write Only) bit
Bit
0
1
2
3
5:4
For details see
For details see
Transmitter Holding Register (when DLAB = 0, Write Only)”
Symbol
FIFOEN
RXFIFO
RES
TXFIFO
RES
DMAMO
DE
-
description
All information provided in this document is subject to legal disclaimers.
Value Description
0
1
0
1
0
1
0
1
Section 10.5.1 “UART Receiver Buffer Register (when DLAB = 0, Read Only)”
Section 10.5.5 “UART Interrupt Identification Register”
Rev. 1 — 15 February 2011
FIFO Enable
UART FIFOs are disabled. Must not be used in the application.
Active high enable for both UART RX and TX FIFOs and FCR[7:1]
access. This bit must be set for proper UART operation. Any
transition on this bit will automatically clear the UART FIFOs.
RX FIFO Reset
No impact on either of UART FIFOs.
Writing a logic 1 to FCR[1] will clear all bytes in UART RX FIFO,
reset the pointer logic. This bit is self-clearing.
TX FIFO Reset
No impact on either of UART FIFOs.
Writing a logic 1 to FCR[2] will clear all bytes in UART TX FIFO,
reset the pointer logic. This bit is self-clearing.
DMA Mode Select. When the FIFO enable bit (bit 0 of this
register) is set, this bit selects the DMA mode. See
Section
DMA not used.
DMA mode enabled.
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
10.5.6.1.
Chapter 10: LPC122x UART1
and
Section 10.5.2 “UART
UM10441
© NXP B.V. 2011. All rights reserved.
166 of 442
Reset
value
0
0
0
0
NA