OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 159

• Manufacturer Part Number: OM13013,598
• Description: BOARD DEMO IAR LPC1227 JLINKLITE
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of OM13013,598

• Design Resources: LPC122x-SK Brd Schematic
• Processor To Be Evaluated: LPC1227
• Processor Series: LPC122x
• Data Bus Width: 32 bit
• Interface Type: UART, SSP, SPI, I2C
• Cpu Core: ARM Cortex-M0
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3 V to 3.6 V
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6885

NXP Semiconductors
UM10441
User manual
The UART transmitter block, TX, accepts data written by the CPU or host and buffers the
data in the UART TX Holding Register FIFO (THR). The UART TX Shift Register (TSR)
reads the data stored in the THR and assembles the data to transmit via the serial output
pin, TXD1.
The UART Baud Rate Generator block, BRG, generates the timing enables used by the
UART TX block. The BRG clock input source is UART_PCLK. The main clock is divided
down per the divisor specified in the DLL and DLM registers. This divided down clock is a
16x oversample clock, NBAUDOUT.
The interrupt interface contains registers IER and IIR. The interrupt interface receives
several one clock wide enables from the TX and RX blocks.
Status information from the TX and RX is stored in the LSR. Control information for the TX
and RX is stored in the LCR.
Fig 9.
U0INTR
UART block diagram
All information provided in this document is subject to legal disclaimers.
INTERRUPT
U0IER
U0IIR
Rev. 1 — 15 February 2011
U0SCR
INTERFACE
Chapter 9: LPC122x UART0 with modem control
APB
U0THR
U0RBR
U0FCR
U0LSR
U0LCR
U0BRG
U0DLM
U0DLL
U0RX
U0TX
U0TSR
U0RSR
UM10441
© NXP B.V. 2011. All rights reserved.
NBAUDOUT
RCLK
RXD
TXD
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