OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 294
OM13013,598
Manufacturer Part Number
OM13013,598
Description
BOARD DEMO IAR LPC1227 JLINKLITE
Manufacturer
NXP Semiconductors
Series
-r
Specifications of OM13013,598
Design Resources
LPC122x-SK Brd Schematic
Processor To Be Evaluated
LPC1227
Processor Series
LPC122x
Data Bus Width
32 bit
Interface Type
UART, SSP, SPI, I2C
Cpu Core
ARM Cortex-M0
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Operating Supply Voltage
3 V to 3.6 V
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-6885
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UM10441
User manual
18.7.4 Interrupts
18.7.5 Comparator outputs
The interrupt can be selected to be edge or level style. If level is selected, the interrupt
leaving this block is synchronized first to the peripheral clock domain to prevent an
asynchronous interrupt path crashing the CPU. If edge level interrupts are selected, a
choice of active high, active low or active both edges can be selected. Interrupts are
cleared by the CPU writing CLINT high.
The combined ORed interrupts of comparator0 and comparator1 are routed to the NVIC
for ISR purposes using the CPU.
The two comparator level outputs are routed to external pins. The level and edge
comparator outputs are also internally connected to the capture inputs of the two 16-bit
timers. The outputs can be selected in synchronous or asynchronous modes (see
Table
In addition, the status of each comparator output can be observed through the comparator
status register bits
The level and edge outputs of each comparator are routed to the two 16-bit timers
internally as listed below:
This feature allows tick-counting on comparator output transitions on either the positive
edge, the negative edge, or both edges (depending on the comparator register
configuration), if the edge capture is chosen. If the timer level capture is chosen, the
counter can run while the comparator output is in a given state.
•
•
•
•
•
For internal connection to the timer capture inputs, synchronous or asynchronous
modes can be selected.
When the asynchronous outputs are routed to external pins, the comparators can be
used without clocking PCLK to save power once the device is configured.
When the comparator is configured to wake up the part from Deep-sleep mode, the
asynchronous mode must be selected.
16-bit timer 0 (CT16B0):
– capture input 3: comparator 0 edge
– capture input 2: comparator 0 level
16-bit timer 1 (CT16B1):
– capture input 3: comparator 1 edge
– capture input 2: comparator 1 level
274):
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 15 February 2011
Chapter 18: LPC122x Comparator
UM10441
© NXP B.V. 2011. All rights reserved.
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