OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 406
OM13013,598
Manufacturer Part Number
OM13013,598
Description
BOARD DEMO IAR LPC1227 JLINKLITE
Manufacturer
NXP Semiconductors
Series
-r
Specifications of OM13013,598
Design Resources
LPC122x-SK Brd Schematic
Processor To Be Evaluated
LPC1227
Processor Series
LPC122x
Data Bus Width
32 bit
Interface Type
UART, SSP, SPI, I2C
Cpu Core
ARM Cortex-M0
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Operating Supply Voltage
3 V to 3.6 V
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-6885
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UM10441
User manual
25.4.7.7.2 Operation
25.4.7.7.3 Restrictions
25.4.7.7.4 Condition flags
25.4.7.7.5 Examples
25.4.7.8.1 Syntax
25.4.7.8.2 Operation
25.4.7.8.3 Restrictions
25.4.7.8.4 Condition flags
25.4.7.8.5 Examples
25.4.7.9.1 Syntax
25.4.7.9.2 Operation
25.4.7.8 NOP
25.4.7.9 SEV
MSR updates one of the special registers with the value from the register specified by Rn.
See
In this instruction, Rn must not be SP and must not be PC.
This instruction updates the flags explicitly based on the value in Rn.
MSR CONTROL, R1 ; Read R1 value and write it to the CONTROL register
No Operation.
NOP
NOP performs no operation and is not guaranteed to be time consuming. The processor
might remove it from the pipeline before it reaches the execution stage.
Use NOP for padding, for example to place the subsequent instructions on a 64-bit
boundary.
There are no restrictions.
This instruction does not change the flags.
Send Event.
SEV
SEV causes an event to be signaled to all processors within a multiprocessor system. It
also sets the local event register, see
spec_reg is the special-purpose destination register: APSR, IPSR, EPSR, IEPSR,
IAPSR, EAPSR, PSR, MSP, PSP, PRIMASK, or CONTROL.
NOP ; No operation
Section
25–25.4.7.6.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 15 February 2011
Section
Chapter 25: LPC122x Appendix ARM Cortex-M0
25–25.3.5.
UM10441
© NXP B.V. 2011. All rights reserved.
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