OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 42

• Manufacturer Part Number: OM13013,598
• Description: BOARD DEMO IAR LPC1227 JLINKLITE
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of OM13013,598

• Design Resources: LPC122x-SK Brd Schematic
• Processor To Be Evaluated: LPC1227
• Processor Series: LPC122x
• Data Bus Width: 32 bit
• Interface Type: UART, SSP, SPI, I2C
• Cpu Core: ARM Cortex-M0
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3 V to 3.6 V
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6885

NXP Semiconductors
UM10441
User manual
4.5.39 Wake-up configuration register
Remark: Reserved bits in this register must always be written as indicated. This register
must be initialized correctly before entering Deep-sleep mode.
Remark: Settings in this register are affected by the WDT lock status: If the watchdog
oscillator is selected as the clock source for the WDT, writes to bit 6 in the PDSLEEPCFG
register are ignored if at the same time bit 5 is set in the WDMOD register (see
Table 48.
The bits in this register can be programmed to indicate the state the microcontroller must
enter when it is waking up from Deep-sleep mode.
Remark: Settings in this register are affected by the WDT lock status:
Bit
2:0
3
5:4
6
15:7
31:16
•
•
frequency must be set to its lowest value (bits FREQSEL in the WDTOSCCTRL =
0001, see
disabled in the SYSAHBCLKCTRL register (see
mode.
Note that the WD oscillator must be running before setting the WDLOCKCLK bit
in the WDMODE register.
The watchdog oscillator, if running, contributes an additional current drain in
Deep-sleep mode.
If the watchdog oscillator is selected as the clock source for the WDT, writes to bit 6 in
the PDAWAKECFG register are ignored if at the same time bit 5 is set in the WDMOD
register (see
If the IRC is selected as the clock source for the WDT, writes to bits 0 and bit 1 in the
PDAWAKECFG register are ignored if at the same time bit 5 is set in the WDMOD
register (see
Symbol
-
BOD_PD
-
WDTOSC_PD
-
-
description
Deep-sleep configuration register (PDSLEEPCFG, address 0x4004 8230) bit
Table
All information provided in this document is subject to legal disclaimers.
Table
Table
13) and all peripheral clocks other than the timer clock must be
Rev. 1 — 15 February 2011
264).
264).
Value
0
1
0
1
-
Description
Reserved. Always write these bits as ones.
BOD power-down control in Deep-sleep mode
Powered
Powered down
Reserved. Always write these bits as ones.
Watchdog oscillator power-down control in
Deep-sleep mode
Powered
Powered down. Must be changed to 0 before the
WDLOCKCLK bit is set in the WDMODE register.
See
Reserved. Always write these bits as ones.
Reserved
Table
Chapter 4: LPC122x System control (SYSCON)
264.
Table
21) before entering Deep-sleep
UM10441
© NXP B.V. 2011. All rights reserved.
Table
42 of 442
Reset
value
111
1
11
1
1 1111
1111
0
264).