OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 382
OM13013,598
Manufacturer Part Number
OM13013,598
Description
BOARD DEMO IAR LPC1227 JLINKLITE
Manufacturer
NXP Semiconductors
Series
-r
Specifications of OM13013,598
Design Resources
LPC122x-SK Brd Schematic
Processor To Be Evaluated
LPC1227
Processor Series
LPC122x
Data Bus Width
32 bit
Interface Type
UART, SSP, SPI, I2C
Cpu Core
ARM Cortex-M0
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Operating Supply Voltage
3 V to 3.6 V
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-6885
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UM10441
User manual
Fig 69. LSR #3
Fig 70. LSL #3
Carry
Flag
31
0
25.4.3.3.3 LSL
25.4.3.3.4 ROR
31
0
0
Logical shift left by n bits moves the right-hand 32-n bits of the register Rm, to the left by n
places, into the left-hand 32-n bits of the result, and it sets the right-hand n bits of the
result to 0. See
You can use the LSL operation to multiply the value in the register Rm by 2
regarded as an unsigned integer or a two’s complement signed integer. Overflow can
occur without warning.
When the instruction is LSLS the carry flag is updated to the last bit shifted out, bit[32-n],
of the register Rm. These instructions do not affect the carry flag when used with LSL #0.
Remark:
Rotate right by n bits moves the left-hand 32-n bits of the register Rm, to the right by n
places, into the right-hand 32-n bits of the result, and it moves the right-hand n bits of the
register into the left-hand n bits of the result. See
When the instruction is RORS the carry flag is updated to the last bit rotation, bit[n-1], of
the register Rm.
Remark:
•
•
•
•
If n is 32 or more, then all the bits in the result are cleared to 0.
If n is 33 or more and the carry flag is updated, it is updated to 0.
If n is 32 or more, then all the bits in the result are cleared to 0.
If n is 33 or more and the carry flag is updated, it is updated to 0.
All information provided in this document is subject to legal disclaimers.
Figure
Rev. 1 — 15 February 2011
70.
...
...
Chapter 25: LPC122x Appendix ARM Cortex-M0
Figure
25–71.
5
5
4
4
3
3
UM10441
2
© NXP B.V. 2011. All rights reserved.
0 0 0
2
1 0
n
, if the value is
1 0
Carry
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