OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 350

• Manufacturer Part Number: OM13013,598
• Description: BOARD DEMO IAR LPC1227 JLINKLITE
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of OM13013,598

• Design Resources: LPC122x-SK Brd Schematic
• Processor To Be Evaluated: LPC1227
• Processor Series: LPC122x
• Data Bus Width: 32 bit
• Interface Type: UART, SSP, SPI, I2C
• Cpu Core: ARM Cortex-M0
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3 V to 3.6 V
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6885

NXP Semiconductors
UM10441
User manual
22.5.1 CRC mode register
22.5.2 CRC seed register
22.5.3 CRC checksum register
22.5.4 CRC data register
Table 347. CRC mode register (MODE, address 0x5007 0000) bit description
Table 348. CRC seed register (SEED, address 0x5007 0004) bit description
This register is a Read-only register containing the most recent checksum.
Table 349. CRC checksum register (SUM, address 0x5007 0008) bit description
This register is a Write-only register containing the data block for which the CRC sum will
be calculated.
Bit
1:0
2
3
4
5
31:6 Reserved
Bit
31:0
Bit
31:0
Symbol
CRC_POLY
BIT_RVS_WR
CMPL_WR
BIT_RVS_SUM
CMPL_SUM
Symbol
CRC_SEED
Symbol
CRC_SUM
All information provided in this document is subject to legal disclaimers.
Description
A write access to this register will load CRC seed value to
CRC_SUM register with selected bit order and 1’s
complement pre-processes.
Remark: A write access to this register will overrule the
CRC calculation in progresses.
Description
The most recent CRC sum can be read through this
register with selected bit order and 1’s complement
post-processes.
Rev. 1 — 15 February 2011
Description
CRC polynom:
1X= CRC-32 polynomial
01= CRC-16 polynomial
00= CRC-CCITT polynomial
Data bit order:
1= Bit order reverse for CRC_WR_DATA (per byte)
0= No bit order reverse for CRC_WR_DATA (per byte)
Data complement:
1= 1’s complement for CRC_WR_DATA
0= No 1’s complement for CRC_WR_DATA
CRC sum bit order:
1= Bit order reverse for CRC_SUM
0= No bit order reverse for CRC_SUM
CRC sum complement:
1= 1’s complement for CRC_SUM
0=No 1’s complement for CRC_SUM
Always 0 when read
Chapter 22: LPC122x CRC engine
UM10441
© NXP B.V. 2011. All rights reserved.
Reset value
0x0000 FFFF
Reset value
0x0000 FFFF
Reset value
00
0
0
0
0
0x0000000
350 of 442