OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 395

• Manufacturer Part Number: OM13013,598
• Description: BOARD DEMO IAR LPC1227 JLINKLITE
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of OM13013,598

• Design Resources: LPC122x-SK Brd Schematic
• Processor To Be Evaluated: LPC1227
• Processor Series: LPC122x
• Data Bus Width: 32 bit
• Interface Type: UART, SSP, SPI, I2C
• Cpu Core: ARM Cortex-M0
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3 V to 3.6 V
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6885

NXP Semiconductors
UM10441
User manual
25.4.5.3.2 Operation
25.4.5.3.3 Restrictions
25.4.5.3.4 Condition flags
25.4.5.3.5 Examples
25.4.5.4.1 Syntax
25.4.5.4 CMP and CMN
where:
The range of shift length depends on the instruction:
ASR — shift length from 1 to 32
LSL — shift length from 0 to 31
LSR — shift length from 1 to 32.
Remark: MOVS Rd, Rm is a pseudonym for LSLS Rd, Rm, #0.
ASR, LSL, LSR, and ROR perform an arithmetic-shift-left, logical-shift-left,
logical-shift-right or a right-rotation of the bits in the register Rm by the number of places
specified by the immediate imm or the value in the least-significant byte of the register
specified by Rs.
For details on what result is generated by the different instructions, see
Section
In these instructions, Rd, Rm, and Rs must only specify R0-R7. For non-immediate
instructions, Rd and Rm must specify the same register.
These instructions update the N and Z flags according to the result.
The C flag is updated to the last bit shifted out, except when the shift length is 0, see
Section
Compare and Compare Negative.
CMN Rn, Rm
CMP Rn, #imm
CMP Rn, Rm
Rd is the destination register. If Rd is omitted, it is assumed to take the same value as
Rm.
Rm is the register holding the value to be shifted.
Rs is the register holding the shift length to apply to the value in Rm.
imm is the shift length.
ASRS
25–25.4.3.3.
25–25.4.3.3. The V flag is left unmodified.
LSLS
LSRS
RORS
R7, R5, #9 ; Arithmetic shift right by 9 bits
All information provided in this document is subject to legal disclaimers.
R1, R2, #3 ; Logical shift left by 3 bits with flag update
R4, R5, #6 ; Logical shift right by 6 bits
R4, R4, R6 ; Rotate right by the value in the bottom byte of R6.
Rev. 1 — 15 February 2011
Chapter 25: LPC122x Appendix ARM Cortex-M0
UM10441
© NXP B.V. 2011. All rights reserved.
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