OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 155

• Manufacturer Part Number: OM13013,598
• Description: BOARD DEMO IAR LPC1227 JLINKLITE
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of OM13013,598

• Design Resources: LPC122x-SK Brd Schematic
• Processor To Be Evaluated: LPC1227
• Processor Series: LPC122x
• Data Bus Width: 32 bit
• Interface Type: UART, SSP, SPI, I2C
• Cpu Core: ARM Cortex-M0
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3 V to 3.6 V
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6885

NXP Semiconductors
UM10441
User manual
9.5.15 UART RS485 Control register
Although
control, it is strongly suggested to let UART hardware implemented auto flow control
features take care of this, and limit the scope of TXEn to software flow control.
TER enables implementation of software and hardware flow control. When TXEn =1,
UART transmitter will keep sending data as long as they are available. As soon as TXEn
becomes 0, UART transmission will stop.
Table 155
Table 155. UART Transmit Enable Register (TER - address 0x4000 8030) bit description
The RS485CTRL register controls the configuration of the UART in RS-485/EIA-485
mode.
Table 156. UART RS485 Control register (RS485CTRL - address 0x4000 804C) bit description
Bit
6:0
7
31:8 -
Bit
0
1
2
Symbol
NMMEN
RXDIS
AADEN
Symbol
-
TXEN
Table 155
describes how to use TXEn bit in order to achieve software flow control.
All information provided in this document is subject to legal disclaimers.
Description
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
When this bit is 1, as it is after a Reset, data written to the THR
is output on the TXD pin as soon as any preceding data has
been sent. If this bit cleared to 0 while a character is being sent,
the transmission of that character is completed, but no further
characters are sent until this bit is set again. In other words, a 0
in this bit blocks the transfer of characters from the THR or TX
FIFO into the transmit shift register. Software can clear this bit
when it detects that the a hardware-handshaking TX-permit
signal (CTS) has gone false, or with software handshaking,
when it receives an XOFF character (DC3). Software can set
this bit again when it detects that the TX-permit signal has gone
true, or when it receives an XON (DC1) character.
Reserved
Value
0
1
0
1
0
1
describes how to use TXEn bit in order to achieve hardware flow
Rev. 1 — 15 February 2011
Description
NMM enable.
RS-485/EIA-485 Normal Multidrop Mode (NMM)
is disabled.
RS-485/EIA-485 Normal Multidrop Mode (NMM)
is enabled. In this mode, an address is detected
when a received byte causes the UART to set the
parity error and generate an interrupt.
Receiver enable.
The receiver is enabled.
The receiver is disabled.
AAD enable.
Auto Address Detect (AAD) is disabled.
Auto Address Detect (AAD) is enabled.
Chapter 9: LPC122x UART0 with modem control
UM10441
© NXP B.V. 2011. All rights reserved.
Reset value
NA
1
-
Reset
value
0
0
0
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