OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 340

• Manufacturer Part Number: OM13013,598
• Description: BOARD DEMO IAR LPC1227 JLINKLITE
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of OM13013,598

• Design Resources: LPC122x-SK Brd Schematic
• Processor To Be Evaluated: LPC1227
• Processor Series: LPC122x
• Data Bus Width: 32 bit
• Interface Type: UART, SSP, SPI, I2C
• Cpu Core: ARM Cortex-M0
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3 V to 3.6 V
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6885

NXP Semiconductors
UM10441
User manual
21.7.4.1 Invalid cycle
21.7.4.2 Basic cycle
21.7.4 DMA cycle types
Table 342. DMA channel priority
The cycle_ctrl bits in the channel control data structure control how the DMA controller
performs a cycle (see
The controller uses four cycle types described in this manual:
See ARM micro DMA (PL230) documentation for additional cycle types.
For all cycle types, the controller arbitrates after 2
channel is set to a large 2
DMA transfer until the low-priority DMA transfer completes. Therefore, the user must take
care when setting the R_power bit in the channel_cfg data structure, that the latency for
high-priority channels is not significantly increased.
After the controller completes a DMA cycle, it sets the cycle type to invalid to prevent it
from repeating the same DMA cycle.
In this mode, the controller can be configured to use either the primary or the alternate
channel control data structure. After the channel is enabled and the controller receives a
request for this channel, the flow for the basic cycle is as follows:
Channel number
0
1
...
20
0
1
...
20
1. The controller performs 2
2. The controller arbitrates:
•
•
•
•
Invalid
Basic
Auto-request
Ping-pong
flow continues at step 3.
– If a higher-priority channel is requesting service then the controller services that
– If the peripheral or software signals a request to the controller then it continues at
channel.
step 1.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 15 February 2011
Table
Chapter 21: LPC122x General purpose micro DMA controller
R
value then it prevents all other channels from performing a
345).
R
Priority level setting
High
High
...
High
Default
Default
...
Default
transfers. If the number of transfers remaining is zero the
R
DMA transfers. If a low-priority
Arbitration priority in
descending order
Highest
Next highest
...
...
...
...
...
Lowest
UM10441
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