OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 81

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OM13013,598

Manufacturer Part Number
OM13013,598
Description
BOARD DEMO IAR LPC1227 JLINKLITE
Manufacturer
NXP Semiconductors
Series
-r
Datasheets

Specifications of OM13013,598

Design Resources
LPC122x-SK Brd Schematic
Processor To Be Evaluated
LPC1227
Processor Series
LPC122x
Data Bus Width
32 bit
Interface Type
UART, SSP, SPI, I2C
Cpu Core
ARM Cortex-M0
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Operating Supply Voltage
3 V to 3.6 V
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-6885
NXP Semiconductors
UM10441
User manual
6.4.18 PIO0_1 register
Table 78.
Table 79.
Bit
6
7
8
9
10
12:11
15:13
31:16
Bit
2:0
3
4
Symbol
INV
-
-
DRV
OD
S_MODE
CLK_DIV
-
Symbol
FUNC
-
MODE
PIO0_0 register (PIO0_0, address 0x4004 4044) bit description
PIO0_1 register (PIO0_1, address 0x4004 4048) bit description
All information provided in this document is subject to legal disclaimers.
Value
0
1
0
1
0
1
0x0
0x1
0x2
0x3
0x0
0x1
0x2
0x3
0x4
0x5
0x6
-
Value
0x0
0x1
0x2
0x3
0x4
0
1
Rev. 1 — 15 February 2011
Description
Invert input
Input not inverted.
Input inverted.
Reserved.
Reserved.
Drive current mode (Normal-drive pin).
2 mA drive current selected.
High mode current selected.
Open-drain mode.
Open-drain mode disabled.
Open-drain mode enabled.
Sample mode
Bypass input filter.
Input pulses shorter than one filter clock are rejected.
Input pulses shorter than two filter clocks are rejected.
Input pulses shorter than three filter clocks are rejected.
Select peripheral clock divider for input filter sampling clock.
IOCONFIGCLKDIV0.
IOCONFIGCLKDIV1.
IOCONFIGCLKDIV2.
IOCONFIGCLKDIV3.
IOCONFIGCLKDIV4.
IOCONFIGCLKDIV5.
IOCONFIGCLKDIV6.
Reserved.
Description
Selects pin function.
Selects function PIO0_1.
Reserved. Do not use.
Select function RXD0.
Select function CT32B0_CAP0.
Select function CT32B0_MAT0.
Reserved
Selects function mode (on-chip pull-up resistor control).
Inactive (pull-up resistor not enabled).
Pull-up resistor enabled.
Chapter 6: LPC122x I/O configuration (IOCONFIG)
UM10441
© NXP B.V. 2011. All rights reserved.
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Reset
value
0
1
0
0
0
00
000
0
Reset
value
000
0
1

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