OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 131

• Manufacturer Part Number: OM13013,598
• Description: BOARD DEMO IAR LPC1227 JLINKLITE
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of OM13013,598

• Design Resources: LPC122x-SK Brd Schematic
• Processor To Be Evaluated: LPC1227
• Processor Series: LPC122x
• Data Bus Width: 32 bit
• Interface Type: UART, SSP, SPI, I2C
• Cpu Core: ARM Cortex-M0
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3 V to 3.6 V
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6885

NXP Semiconductors
Table 121. Register overview: GPIO (base address port 0: 0x5000 0000; port 1: 0x5001 0000, port 2: 0x5002 0000)
UM10441
User manual
Name
MASK
PIN
OUT
SET
CLR
NOT
DIR
IS
IBE
IEV
IE
RIS
MIS
IC
-
8.3.1 GPIO mask register
8.3.2 GPIO pin value register
Access
R/W
R
R/W
W
W
W
R/W
R/W
R/W
R/W
R/W
R
R
W
-
This register masks the read and/or write accesses to the following masked registers:
PIN, OUT, SET, CLR, and NOT. Only bits set to 0 in the MASK register enable the
corresponding bits in the masked registers to be changed or their value to be read.
Setting any mask bit to 0 allows the pin output to be changed by write operations to the
pin’s OUT, SET, CLR, and NOT registers. The current state of the pin can be read from the
PIN registers and the current value of the OUT registers can be read.
Setting any mask bit to 1 allows write operations to the pin’s OUT, SET, CLR, and NOT
registers to have no effect on the pin’s output level. Read operations return 0 regardless of
the pin’s level or the value of the OUT register.
Table 122. GPIO mask register (MASK - address 0x5000 0000 (GPIO0), 0x5001 0000 (GPIO1),
This register provides the current logic state of port pins that are configured to perform
digital functions. A read operation on this register will return the logic value of the pin
regardless of whether the pin is configured for input or output, or whether it is configured
as GPIO or any other applicable alternate digital function. As an example, a particular port
Bit
31:0
Address
offset
0x000
0x004
0x008
0x00C
0x010
0x014
0x020
0x024
0x028
0x02C
0x030
0x034
0x038
0x03C
0x040
Symbol
MASK
0x5002 0000 (GPIO2)) bit description
Description
Pin value mask register. Affects operations on PIN, OUT, SET,
CLR, and NOT registers.
Pin value register.
Pin output value register.
Pin output value set register.
Pin output value clear register.
Pin output value invert register.
Data direction register.
Interrupt sense register.
Interrupt both edges register.
Interrupt event register.
Interrupt mask register.
Raw interrupt status register.
Masked interrupt status register.
Interrupt clear register.
Reserved.
All information provided in this document is subject to legal disclaimers.
Description
GPIO pin PIOn_x access control.
0 = read/write not masked. 1 = read/write masked.
Rev. 1 — 15 February 2011
Chapter 8: LPC122x General Purpose I/O (GPIO)
UM10441
© NXP B.V. 2011. All rights reserved.
Reset
value
0x0
Reset value
0x0000 0000
configuration
dependent
0x0000 0000
n/a
n/a
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
Access
R/W
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