OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 281

• Manufacturer Part Number: OM13013,598
• Description: BOARD DEMO IAR LPC1227 JLINKLITE
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of OM13013,598

• Design Resources: LPC122x-SK Brd Schematic
• Processor To Be Evaluated: LPC1227
• Processor Series: LPC122x
• Data Bus Width: 32 bit
• Interface Type: UART, SSP, SPI, I2C
• Cpu Core: ARM Cortex-M0
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3 V to 3.6 V
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6885

NXP Semiconductors
Table 264. Watchdog Mode register (MOD - 0x4000 4000) bit description
UM10441
User manual
Bit
0
1
2
3
4
Symbol
WDEN
WDRESET
WDTOF
WDINT
WDPROTECT
17.7.1 Watchdog Mode register
Value
0
1
0
1
0
1
Table 263. Register overview: Watchdog timer (base address 0x4000 4000)
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The MOD register controls the operation of the Watchdog as per the combination of
WDEN and RESET bits.
Watchdog reset or interrupt will occur any time the watchdog is running and has an
operating clock source. If a watchdog interrupt occurs in Sleep mode, it will wake up the
device.
Name
CLKSEL
WARNINT
WINDOW
Reset value reflects the data stored in used bits only. It does not include reserved bits content.
Watchdog enable bit. The WDEN bit can be locked from subsequent writes
The watchdog timer is stopped.
A watchdog time-out will cause an interrupt.
The Watchdog interrupt flag is set when the Watchdog counter reaches the
Description
by the WDLOCKEN bit.
The watchdog timer is running. The watchdog timer is automatically enabled
at reset without requiring a valid feed sequence. Any subsequent writes to
this bit require a valid feed sequence before the change can take effect.
Watchdog reset enable bit. This bit can be changed at any time. The
WDRESET bit is set by an external reset or a Watchdog timer reset. The
WDRESET bit can be locked from subsequent writes by the WDLOCKEN
bit.
A watchdog timeout will cause a chip reset.
Watchdog time-out flag. The Watchdog time-out flag is set when the
Watchdog times out, when a feed error occurs, or when WDPROTECT =1
and an attempt is made to write to the WDTC register. This flag is cleared by
software writing a 0 to this bit. Causes a chip reset if WDRESET = 1.
value specified by WDWARNINT. This flag is cleared when any reset occurs,
and is cleared by software by writing a 1 to this bit.
Watchdog update mode. This bit is Set Only. Once the WDPROTECT bit is
set it can not be cleared by software. The WDPROTECT bit is cleared by an
external reset or a Watchdog timer reset.
The watchdog timer constant value (WDTC) can be changed at any time.
The watchdog timer constant value (WDTC) can be changed only after the
counter is below the value of WARNINT and WINDOW.
Access Address
R/W
R/W
R/W
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 15 February 2011
offset
0x010
0x014
0x018
Chapter 17: LPC122x Windowed Watchdog Timer (WWDT)
Description
Watchdog clock source selection register.
Watchdog Warning Interrupt compare value.
Watchdog Window compare value.
UM10441
© NXP B.V. 2011. All rights reserved.
Reset value
1
1
0 (Only after
external reset)
0
0
0
0
0xFF FFFF
Reset
value
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