OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 207

• Manufacturer Part Number: OM13013,598
• Description: BOARD DEMO IAR LPC1227 JLINKLITE
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of OM13013,598

• Design Resources: LPC122x-SK Brd Schematic
• Processor To Be Evaluated: LPC1227
• Processor Series: LPC122x
• Data Bus Width: 32 bit
• Interface Type: UART, SSP, SPI, I2C
• Cpu Core: ARM Cortex-M0
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3 V to 3.6 V
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6885

NXP Semiconductors
Table 199. Master Transmitter mode
UM10441
User manual
STAT
Status
Code
0x08
0x10
0x18
0x20
0x28
0x30
0x38
Status of the
I
hardware
A START condition
has been transmitted.
A repeated START
condition has been
transmitted.
SLA+W has been
transmitted; ACK has
been received.
SLA+W has been
transmitted; NOT
ACK has been
received.
Data byte in DAT has
been transmitted;
ACK has been
received.
Data byte in DAT has
been transmitted;
NOT ACK has been
received.
Arbitration lost in
SLA+R/W or Data
bytes.
2
11.10.5 Detailed state tables
C-bus and
The following tables show detailed state information for the four I
Application software response
To/From DAT
Load SLA+W; clear
STA
Load SLA+W or
Load SLA+R; Clear
STA
Load data byte or
No DAT action or
No DAT action or
No DAT action
Load data byte or
No DAT action or
No DAT action or
No DAT action
Load data byte or
No DAT action or
No DAT action or
No DAT action
Load data byte or
No DAT action or
No DAT action or
No DAT action
No DAT action or
No DAT action
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 15 February 2011
To CON
STA STO SI
X
X
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AA
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Chapter 11: LPC122x I2C-bus controller
SLA+W will be transmitted; ACK bit will
Repeated START will be transmitted.
STOP condition followed by a START
be received.
Repeated START will be transmitted.
flag will be reset.
STOP condition followed by a START
condition will be transmitted; STO flag will
be reset.
be received.
Repeated START will be transmitted.
flag will be reset.
STOP condition followed by a START
condition will be transmitted; STO flag will
be reset.
Data byte will be transmitted; ACK bit will
be received.
Repeated START will be transmitted.
flag will be reset.
STOP condition followed by a START
condition will be transmitted; STO flag will
be reset.
I
Next action taken by I
be received.
As above.
SLA+W will be transmitted; the I
will be switched to MST/REC mode.
Data byte will be transmitted; ACK bit will
be received.
STOP condition will be transmitted; STO
flag will be reset.
condition will be transmitted; STO flag will
be reset.
Data byte will be transmitted; ACK bit will
STOP condition will be transmitted; STO
Data byte will be transmitted; ACK bit will
STOP condition will be transmitted; STO
STOP condition will be transmitted; STO
slave will be entered.
A START condition will be transmitted
when the bus becomes free.
2
C-bus will be released; not addressed
2
C operating modes.
UM10441
© NXP B.V. 2011. All rights reserved.
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C hardware
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