OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 262

• Manufacturer Part Number: OM13013,598
• Description: BOARD DEMO IAR LPC1227 JLINKLITE
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of OM13013,598

• Design Resources: LPC122x-SK Brd Schematic
• Processor To Be Evaluated: LPC1227
• Processor Series: LPC122x
• Data Bus Width: 32 bit
• Interface Type: UART, SSP, SPI, I2C
• Cpu Core: ARM Cortex-M0
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3 V to 3.6 V
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6885

NXP Semiconductors
Table 243: Capture Control Register (CCR, address 0x4001 8028 (CT32B0) and 0x4001 C028 (CT32B1)) bit
UM10441
User manual
Bit
9
10
11
31:12 -
Symbol
CAP3RE
CAP3FE
CAP3I
description
14.7.10 External Match Register
14.7.9 Capture Register
Value Description
1
0
1
0
1
0
Each Capture register is associated with a device pin and may be loaded with the Timer
Counter value when a specified event occurs on that pin. The settings in the Capture
Control Register register determine whether the capture function is enabled, and whether
a capture event happens on the rising edge of the associated pin, the falling edge, or on
both edges.
Table 244: Capture registers (CR0 to 3, addresses 0x4001 802C to 38 (CT32B0) and
The External Match Register provides both control and status of the external match pins
CAP32Bn_MAT[3:0].
Match events for Match 0 and Match 1 in each timer can cause a DMA request.
If the match outputs are configured as PWM output, the function of the external match
registers is determined by the PWM rules
controlled PWM outputs” on page
Bit
31:0
Capture on CT32Bn_CAP3 rising edge: a sequence of 0 then 1 on CT32Bn_CAP3 will
cause CR3 to be loaded with the contents of TC.
Enabled.
Disabled.
Capture on CT32Bn_CAP3 falling edge: a sequence of 1 then 0 on CT32Bn_CAP3 will
cause CR3 to be loaded with the contents of TC.
Enabled.
Disabled.
Interrupt on CT32Bn_CAP3 event: a CR3 load due to a CT32Bn_CAP3 event will
generate an interrupt.
Enabled.
Disabled.
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
Symbol
CAP
0x4001 C02C to 38 (CT32B1)) bit description
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 15 February 2011
Description
Timer counter capture value.
Chapter 14: LPC122x 32-bit Counter/timer 0/1 (CT32B0/1)
267).
(Section 14.7.13 “Rules for single edge
UM10441
© NXP B.V. 2011. All rights reserved.
262 of 442
Reset
value
0
0
0
NA
Reset
value
0