OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 419

• Manufacturer Part Number: OM13013,598
• Description: BOARD DEMO IAR LPC1227 JLINKLITE
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of OM13013,598

• Design Resources: LPC122x-SK Brd Schematic
• Processor To Be Evaluated: LPC1227
• Processor Series: LPC122x
• Data Bus Width: 32 bit
• Interface Type: UART, SSP, SPI, I2C
• Cpu Core: ARM Cortex-M0
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3 V to 3.6 V
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6885

NXP Semiconductors
UM10441
User manual
25.5.3.7.1 System Handler Priority Register 2
25.5.3.7.2 System Handler Priority Register 3
25.5.3.7 System Handler Priority Registers
Table 387. CCR bit assignments
The SHPR2-SHPR3 registers set the priority level, 0 to 3, of the exception handlers that
have configurable priority.
SHPR2-SHPR3 are word accessible. See the register summary in
attributes.
To access to the system exception priority level using CMSIS, use the following CMSIS
functions:
The input parameter IRQn is the IRQ number, see
The system fault handlers, and the priority field and register for each handler are:
Table 388. System fault handler priority fields
Each PRI_N field is 8 bits wide, but the processor implements only bits[7:6] of each field,
and bits[5:0] read as zero and ignore writes.
The bit assignments are:
Table 389. SHPR2 register bit assignments
The bit assignments are:
Bits
[31:10]
[9]
[8:4]
[3]
[2:0]
Handler
SVCall
PendSV
SysTick
Bits
[31:24]
[23:0]
•
•
uint32_t NVIC_GetPriority(IRQn_Type IRQn)
void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-
STKALIGN
-
UNALIGN_TRP
-
Name
Field
PRI_11
PRI_14
PRI_15
All information provided in this document is subject to legal disclaimers.
Name
PRI_11
-
Rev. 1 — 15 February 2011
Function
Reserved.
Always reads as one, indicates 8-byte stack alignment on
exception entry.
On exception entry, the processor uses bit[9] of the stacked PSR
to indicate the stack alignment. On return from the exception it
uses this stacked bit to restore the correct stack alignment.
Reserved.
Always reads as one, indicates that all unaligned accesses
generate a HardFault.
Reserved.
Register description
Section 25–25.5.3.7.1
Section 25–25.5.3.7.2
Function
Priority of system handler 11, SVCall
Reserved
Chapter 25: LPC122x Appendix ARM Cortex-M0
Table 25–361
for more information.
Table 25–382
UM10441
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