OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 191

• Manufacturer Part Number: OM13013,598
• Description: BOARD DEMO IAR LPC1227 JLINKLITE
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of OM13013,598

• Design Resources: LPC122x-SK Brd Schematic
• Processor To Be Evaluated: LPC1227
• Processor Series: LPC122x
• Data Bus Width: 32 bit
• Interface Type: UART, SSP, SPI, I2C
• Cpu Core: ARM Cortex-M0
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3 V to 3.6 V
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6885

NXP Semiconductors
UM10441
User manual
11.8.2 Master Receiver mode
slave mode. The STA, STO and SI bits must be 0. The SI bit is cleared by writing 1 to the
SIC bit in the CONCLR register. THe STA bit should be cleared after writing the slave
address.
Table 194. CONSET used to configure Master mode
The first byte transmitted contains the slave address of the receiving device (7 bits) and
the data direction bit. In this mode the data direction bit (R/W) should be 0 which means
Write. The first byte transmitted contains the slave address and Write bit. Data is
transmitted 8 bits at a time. After each byte is transmitted, an acknowledge bit is received.
START and STOP conditions are output to indicate the beginning and the end of a serial
transfer.
The I
I
condition is transmitted, the SI bit is set, and the status code in the STAT register is 0x08.
This status code is used to vector to a state service routine which will load the slave
address and Write bit to the DAT register, and then clear the SI bit. SI is cleared by writing
a 1 to the SIC bit in the CONCLR register.
When the slave address and R/W bit have been transmitted and an acknowledgment bit
has been received, the SI bit is set again, and the possible status codes now are 0x18,
0x20, or 0x38 for the master mode, or 0x68, 0x78, or 0xB0 if the slave mode was enabled
(by setting AA to 1). The appropriate actions to be taken for each of these status codes
are shown in
In the master receiver mode, data is received from a slave transmitter. The transfer is
initiated in the same way as in the master transmitter mode. When the START condition
has been transmitted, the interrupt service routine must load the slave address and the
data direction bit to the I
data direction bit (R/W) should be 1 to indicate a read.
2
Bit
Symbol
Value
Fig 14. Format in the Master Transmitter mode
C logic will send the START condition as soon as the bus is free. After the START
S
from Master to Slave
from Slave to Master
2
C interface will enter master transmitter mode when software sets the STA bit. The
SLAVE ADDRESS
7
-
-
Table 199
All information provided in this document is subject to legal disclaimers.
6
I2EN
1
Rev. 1 — 15 February 2011
to
2
C Data register (DAT), and then clear the SI bit. In this case, the
Table
RW=0
5
STA
0
202.
A
4
STO
0
DATA
Chapter 11: LPC122x I2C-bus controller
A = Acknowledge (SDA low)
A = Not acknowledge (SDA high)
S = START condition
P = STOP condition
3
SI
0
n bytes data transmitted
A
2
AA
0
DATA
UM10441
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© NXP B.V. 2011. All rights reserved.
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