OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 396

• Manufacturer Part Number: OM13013,598
• Description: BOARD DEMO IAR LPC1227 JLINKLITE
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of OM13013,598

• Design Resources: LPC122x-SK Brd Schematic
• Processor To Be Evaluated: LPC1227
• Processor Series: LPC122x
• Data Bus Width: 32 bit
• Interface Type: UART, SSP, SPI, I2C
• Cpu Core: ARM Cortex-M0
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3 V to 3.6 V
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6885

NXP Semiconductors
UM10441
User manual
25.4.5.4.2 Operation
25.4.5.4.3 Restrictions
25.4.5.4.4 Condition flags
25.4.5.4.5 Examples
25.4.5.5.1 Syntax
25.4.5.5 MOV and MVN
where:
These instructions compare the value in a register with either the value in another register
or an immediate value. They update the condition flags on the result, but do not write the
result to a register.
The CMP instruction subtracts either the value in the register specified by Rm, or the
immediate imm from the value in Rn and updates the flags. This is the same as a SUBS
instruction, except that the result is discarded.
The CMN instruction adds the value of Rm to the value in Rn and updates the flags. This
is the same as an ADDS instruction, except that the result is discarded.
For the:
These instructions update the N, Z, C and V flags according to the result.
Move and Move NOT.
MOV{S} Rd, Rm
MOVS Rd, #imm
MVNS Rd, Rm
where:
•
•
Rn is the register holding the first operand.
Rm is the register to compare with.
imm is the immediate value to compare with.
S is an optional suffix. If S is specified, the condition code flags are updated on the
result of the operation, see
Rd is the destination register.
CMN
CMP instruction:
– Rn and Rm can specify R0-R14
– immediate must be in the range 0-255.
CMP
instruction Rn, and Rm must only specify R0-R7.
CMN
R2, R9
All information provided in this document is subject to legal disclaimers.
R0, R2
Rev. 1 — 15 February 2011
Section
25–25.4.3.6.
Chapter 25: LPC122x Appendix ARM Cortex-M0
UM10441
© NXP B.V. 2011. All rights reserved.
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