OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 244
OM13013,598
Manufacturer Part Number
OM13013,598
Description
BOARD DEMO IAR LPC1227 JLINKLITE
Manufacturer
NXP Semiconductors
Series
-r
Specifications of OM13013,598
Design Resources
LPC122x-SK Brd Schematic
Processor To Be Evaluated
LPC1227
Processor Series
LPC122x
Data Bus Width
32 bit
Interface Type
UART, SSP, SPI, I2C
Cpu Core
ARM Cortex-M0
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Operating Supply Voltage
3 V to 3.6 V
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-6885
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Table 225. Match Control Register (MCR, address 0x4001 0014 (CT16B0) and 0x4001 4014 (CT16B1)) bit description
UM10441
User manual
Bit
1
2
3
4
5
6
7
8
9
10
11
31:12
Symbol Value Description
MR0R
MR0S
MR1I
MR1R
MR1S
MR2I
MR2R
MR2S
MR3I
MR3R
MR3S
-
…continued
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Reset on MR0: the TC will be reset if MR0 matches it.
Enabled
Disabled
Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches
the TC.
Enabled
Disabled
Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC.
Enabled
Disabled
Reset on MR1: the TC will be reset if MR1 matches it.
Enabled
Disabled
Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches
the TC.
Enabled
Disabled
Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC.
Enabled
Disabled
Reset on MR2: the TC will be reset if MR2 matches it.
Enabled
Disabled
Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches
the TC.
Enabled
Disabled
Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC.
Enabled
Disabled
Reset on MR3: the TC will be reset if MR3 matches it.
Enabled
Disabled
Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches
the TC.
Enabled
Disabled
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 15 February 2011
Chapter 13: LPC122x 16-bit Counter/timer 0/1 (CT16B0/1)
UM10441
© NXP B.V. 2011. All rights reserved.
244 of 442
Reset
value
0
0
0
0
0
0
0
0
0
0
0
NA
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