OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 14

• Manufacturer Part Number: OM13013,598
• Description: BOARD DEMO IAR LPC1227 JLINKLITE
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of OM13013,598

• Design Resources: LPC122x-SK Brd Schematic
• Processor To Be Evaluated: LPC1227
• Processor Series: LPC122x
• Data Bus Width: 32 bit
• Interface Type: UART, SSP, SPI, I2C
• Cpu Core: ARM Cortex-M0
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3 V to 3.6 V
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6885

NXP Semiconductors
UM10441
User manual
Table 6.
Name
-
IOCONFIGCLKDIV6 R/W
IOCONFIGCLKDIV5 R/W
IOCONFIGCLKDIV4 R/W
IOCONFIGCLKDIV3 R/W
IOCONFIGCLKDIV2 R/W
IOCONFIGCLKDIV1 R/W
IOCONFIGCLKDIV0 R/W
BODCTRL
SYSTCKCAL
AHBPRIO
-
IRQLATENCY
INTNMI
-
STARTAPRP0
STARTERP0
STARTRSRP0CLR
STARTSRP0
STARTAPRP1
STARTERP1
STARTRSRP1CLR
STARTSRP1
-
PDSLEEPCFG
Register overview: system control block (base address 0x4004 8000)
All information provided in this document is subject to legal disclaimers.
-
R/W
R/W
W
Access Address
-
R/W
R/W
-
R/W
-
R/W
R
R/W
R/W
W
R
-
R/W
Rev. 1 — 15 February 2011
offset
0x108 -
0x130
0x134
0x138
0x134
0x140
0x144
0x148
0x14C
0x150
0x154
0x158
0x15C -
0x16C
0x170
0x174
0x178 -
0x1FC
0x200
0x204
0x208
0x20C
0x210
0x214
0x218
0x21C
0x220 -
0x22C
0x230
Chapter 4: LPC122x System control (SYSCON)
Description
Reserved
Peripheral clock 6 to the IOCONFIG
block for programmable glitch filter
Peripheral clock 5 to the IOCONFIG
block for programmable glitch filter
Peripheral clock 4 to the IOCONFIG
block for programmable glitch filter
Peripheral clock 3 to the IOCONFIG
block for programmable glitch filter
Peripheral clock 2 to the IOCONFIG
block for programmable glitch filter
Peripheral clock 1 to the IOCONFIG
block for programmable glitch filter
Peripheral clock 0 to the IOCONFIG
block for programmable glitch filter
BOD control
System tick counter calibration
AHB priority setting
Reserved
IQR delay. Allows trade-off between
interrupt latency and determinism.
NMI interrupt source configuration
control
Reserved
Start logic edge control register 0
Start logic signal enable register 0
Start logic reset register 0
Start logic status register 0
Start logic edge control register 1;
peripheral interrupts
Start logic signal enable register 1;
peripheral interrupts
Start logic reset register 1; peripheral
interrupts
Start logic status register 1;
peripheral interrupts
Reserved
Power-down states in Deep-sleep
mode
UM10441
© NXP B.V. 2011. All rights reserved.
Reset value
-
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
not affected by
system reset
0x0000 001F
0x0000 0004
-
0x0000 0010
0x0000 003F
-
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
-
0x0000 FFFF
…continued
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