OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 433

• Manufacturer Part Number: OM13013,598
• Description: BOARD DEMO IAR LPC1227 JLINKLITE
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of OM13013,598

• Design Resources: LPC122x-SK Brd Schematic
• Processor To Be Evaluated: LPC1227
• Processor Series: LPC122x
• Data Bus Width: 32 bit
• Interface Type: UART, SSP, SPI, I2C
• Cpu Core: ARM Cortex-M0
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3 V to 3.6 V
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6885

NXP Semiconductors
26.6 Contents
Chapter 1: LPC122x Introductory information
1.1
1.2
1.3
Chapter 2: LPC122x Memory map
2.1
2.2
Chapter 3: LPC122x Nested Vectored Interrupt Controller (NVIC)
3.1
3.2
Chapter 4: LPC122x System control (SYSCON)
4.1
4.2
4.3
4.4
4.5
4.5.1
4.5.2
4.5.3
4.5.4
4.5.5
4.5.6
4.5.7
4.5.8
4.5.9
4.5.10
4.5.11
4.5.12
4.5.13
4.5.14
4.5.15
4.5.16
4.5.17
4.5.18
4.5.19
4.5.20
4.5.21
4.5.22
4.5.23
4.5.24
4.5.25
4.5.26
4.5.27
4.5.28
4.5.29
4.5.30
4.5.31
UM10441
User manual
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Ordering information . . . . . . . . . . . . . . . . . . . . . 5
How to read this chapter . . . . . . . . . . . . . . . . . . 7
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
How to read this chapter . . . . . . . . . . . . . . . . . . 9
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
How to read this chapter . . . . . . . . . . . . . . . . . 11
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 11
General description . . . . . . . . . . . . . . . . . . . . . 11
Register description . . . . . . . . . . . . . . . . . . . . 12
System memory remap register . . . . . . . . . . . 15
Peripheral reset control register . . . . . . . . . . . 16
System PLL control register . . . . . . . . . . . . . . 17
System PLL status register. . . . . . . . . . . . . . . 17
System oscillator control register . . . . . . . . . . 18
Watchdog oscillator control register . . . . . . . . 18
Internal resonant crystal control register. . . . . 19
System reset status register . . . . . . . . . . . . . . 19
System PLL clock source select register . . . . 20
System PLL clock source update enable
register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Main clock source select register . . . . . . . . . . 21
Main clock source update enable register . . . 21
System AHB clock divider register . . . . . . . . . 21
System AHB clock control register . . . . . . . . . 22
SSP clock divider register. . . . . . . . . . . . . . . . 24
UART0 clock divider register . . . . . . . . . . . . . 24
UART1 clock divider register . . . . . . . . . . . . . 25
RTC clock divider register. . . . . . . . . . . . . . . . 25
CLKOUT clock source select register. . . . . . . 25
CLKOUT clock source update enable register 26
CLKOUT clock divider register . . . . . . . . . . . . 26
POR captured PIO status register 0 . . . . . . . . 26
POR captured PIO status register 1 . . . . . . . . 27
IOCONFIG clock divider registers 0 to 6 . . . . 27
BOD control register . . . . . . . . . . . . . . . . . . . . 27
System tick counter calibration register . . . . . 28
AHB matrix master priority register. . . . . . . . . 28
IRQ latency register . . . . . . . . . . . . . . . . . . . . 29
NMI interrupt source configuration register. . . 29
Start logic edge control register 0 . . . . . . . . . . 30
Start logic signal enable register 0 . . . . . . . . . 31
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 15 February 2011
1.3.1
1.4
2.3
3.3
3.4
4.5.32
4.5.33
4.5.34
4.5.35
4.5.36
4.5.37
4.5.38
4.5.39
4.5.40
4.5.41
4.5.42
4.6
4.7
4.7.1
4.7.1.1
4.7.2
4.7.2.1
4.7.2.2
4.7.2.3
4.7.3
4.7.3.1
4.7.3.2
4.7.3.3
4.7.4
4.7.4.1
4.7.4.2
4.7.4.3
4.8
4.8.1
4.8.2
4.8.3
4.9
4.9.1
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Memory allocation. . . . . . . . . . . . . . . . . . . . . . . 8
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . . 9
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Power management . . . . . . . . . . . . . . . . . . . . 46
Deep-sleep mode details . . . . . . . . . . . . . . . . 50
Deep power-down mode details . . . . . . . . . . 51
Part option summary . . . . . . . . . . . . . . . . . . . . 5
Start logic reset register 0 . . . . . . . . . . . . . . . 32
Start logic status register 0 . . . . . . . . . . . . . . 33
Start logic edge control register 1 . . . . . . . . . 34
Start logic signal enable register 1 . . . . . . . . . 37
Start logic reset register 1 . . . . . . . . . . . . . . . 38
Start logic status register 1 . . . . . . . . . . . . . . 40
Deep-sleep mode configuration register . . . . 41
Wake-up configuration register . . . . . . . . . . . 42
Power-down configuration register . . . . . . . . 43
Device ID register . . . . . . . . . . . . . . . . . . . . . 45
Flash configuration register . . . . . . . . . . . . . . 45
Active mode . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Power configuration in Active mode. . . . . . . . 46
Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Power configuration in Sleep mode . . . . . . . . 47
Programming Sleep mode . . . . . . . . . . . . . . . 47
Wake-up from Sleep mode . . . . . . . . . . . . . . 47
Deep-sleep mode. . . . . . . . . . . . . . . . . . . . . . 47
Power configuration in Deep-sleep mode . . . 48
Programming Deep-sleep mode . . . . . . . . . . 48
Wake-up from Deep-sleep mode . . . . . . . . . . 49
Deep power-down mode . . . . . . . . . . . . . . . . 49
Power configuration in Deep power-down
mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Programming Deep power-down mode . . . . . 49
Wake-up from Deep power-down mode . . . . 50
IRC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . 50
Using external pins to wake up from Deep-sleep
mode (start logic 0) . . . . . . . . . . . . . . . . . . . . 50
Using the RTC to wake up from Deep-sleep mode
(start logic 1) . . . . . . . . . . . . . . . . . . . . . . . . . 51
Using the WAKEUP pin to wake up from Deep
power-down mode . . . . . . . . . . . . . . . . . . . . . 51
Chapter 26: Supplementary information
UM10441
© NXP B.V. 2011. All rights reserved.
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