OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 27

• Manufacturer Part Number: OM13013,598
• Description: BOARD DEMO IAR LPC1227 JLINKLITE
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of OM13013,598

• Design Resources: LPC122x-SK Brd Schematic
• Processor To Be Evaluated: LPC1227
• Processor Series: LPC122x
• Data Bus Width: 32 bit
• Interface Type: UART, SSP, SPI, I2C
• Cpu Core: ARM Cortex-M0
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3 V to 3.6 V
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6885

NXP Semiconductors
UM10441
User manual
4.5.23 POR captured PIO status register 1
4.5.24 IOCONFIG clock divider registers 0 to 6
4.5.25 BOD control register
Table 29.
The PIOPORCAP1 register captures the state (HIGH or LOW) of the PIO pins of port 2
(PIO2_8 to PIO2_11) at power-on-reset. Each bit represents the reset state of one PIO
pin. This register is a read-only status register.
Table 30.
These registers individually configure the seven peripheral input clocks to the IOCONFIG
programmable glitch filter. The clocks can be shut down by setting the DIV bits to 0x0.
Table 31.
The BOD control register selects three separate threshold values for sending a BOD
interrupt to the NVIC and for forced reset. Reset and interrupt threshold values listed in
Table 32
The reset value of the BODCTRL register is not affected by a system reset. Instead, the
BODCTRL register retains its last programmed value.
The BOD control circuit is only reset by POR.
Bit
31:0
Bit
31:0
Bit
7:0
31:8
Symbol
PIOSTAT
Symbol
PIOSTAT
Symbol
DIV
-
are typical values.
POR captured PIO status registers 0 (PIOPORCAP0, address 0x4004 8100) bit
description
POR captured PIO status registers 1 (PIOPORCAP1, address 0x4004 8104) bit
description
IOCONFIG filter clock divider registers 0 to 6 (IOCONFIGCLKDIV0 to
IOCONFIGCLKDIV6, address 4004 8014C to 4004 80134) bit description
All information provided in this document is subject to legal disclaimers.
Description
IOCONFIG filter clock divider values
0: Disable IOCONFIGCLK.
1: Divide by 1.
to
255: Divide by 255.
Reserved
Rev. 1 — 15 February 2011
Description
Raw reset status input PIO0_31
to PIO2_7
Description
Raw reset status input PIO2_8 to
PIO2_11
Chapter 4: LPC122x System control (SYSCON)
Reset value
User implementation dependent
Reset value
User implementation dependent
UM10441
© NXP B.V. 2011. All rights reserved.
Reset value
0
0x00
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