OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 296

• Manufacturer Part Number: OM13013,598
• Description: BOARD DEMO IAR LPC1227 JLINKLITE
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of OM13013,598

• Design Resources: LPC122x-SK Brd Schematic
• Processor To Be Evaluated: LPC1227
• Processor Series: LPC122x
• Data Bus Width: 32 bit
• Interface Type: UART, SSP, SPI, I2C
• Cpu Core: ARM Cortex-M0
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3 V to 3.6 V
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6885

NXP Semiconductors
19.6 Register description
Table 277. Register overview: ADC (base address 0x4002 0000)
UM10441
User manual
Name
CR
GDR
-
INTEN
DR0
DR1
DR2
DR3
DR4
DR5
DR6
DR7
STAT
TRM
Access Address
R/W
R/W
-
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
R/W
19.6.1 A/D Control Register
offset
0x000
0x004
0x008
0x00C
0x010
0x014
0x018
0x01C
0x020
0x024
0x028
0x02C
0x030
0x034
The ADC function must be selected via the IOCON registers in order to get accurate
voltage readings on the monitored pin. For a pin hosting an ADC input, it is not possible to
have a have a digital function selected and yet get valid ADC readings. An inside circuit
disconnects ADC hardware from the associated pin whenever a digital function is selected
on that pin.
The A/D Control Register provides bits to select A/D channels to be converted, A/D timing,
A/D modes, and the A/D start trigger.
Description
A/D Control Register. The CR register must be written to select the
operating mode before A/D conversion can occur.
A/D Global Data Register. Contains the result of the most recent A/D
conversion.
reserved
A/D Interrupt Enable Register. This register contains enable bits that allow
the DONE flag of each A/D channel to be included or excluded from
contributing to the generation of an A/D interrupt.
A/D Channel 0 Data Register. This register contains the result of the most
recent conversion completed on channel 0
A/D Channel 1 Data Register. This register contains the result of the most
recent conversion completed on channel 1.
A/D Channel 2 Data Register. This register contains the result of the most
recent conversion completed on channel 2.
A/D Channel 3 Data Register. This register contains the result of the most
recent conversion completed on channel 3.
A/D Channel 4 Data Register. This register contains the result of the most
recent conversion completed on channel 4.
A/D Channel 5 Data Register. This register contains the result of the most
recent conversion completed on channel 5.
A/D Channel 6 Data Register. This register contains the result of the most
recent conversion completed on channel 6.
A/D Channel 7 Data Register. This register contains the result of the most
recent conversion completed on channel 7.
A/D Status Register. This register contains DONE and OVERRUN flags for
all of the A/D channels, as well as the A/D interrupt flag.
A/D trim register
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 15 February 2011
Chapter 19: LPC122x ADC
UM10441
© NXP B.V. 2011. All rights reserved.
Reset value
0x0000 0000
NA
-
0x0000 0100
NA
NA
NA
NA
NA
NA
NA
NA
0
0
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