OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 418

• Manufacturer Part Number: OM13013,598
• Description: BOARD DEMO IAR LPC1227 JLINKLITE
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of OM13013,598

• Design Resources: LPC122x-SK Brd Schematic
• Processor To Be Evaluated: LPC1227
• Processor Series: LPC122x
• Data Bus Width: 32 bit
• Interface Type: UART, SSP, SPI, I2C
• Cpu Core: ARM Cortex-M0
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3 V to 3.6 V
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6885

NXP Semiconductors
UM10441
User manual
25.5.3.5 System Control Register
25.5.3.6 Configuration and Control Register
Table 385. AIRCR bit assignments
The SCR controls features of entry to and exit from low power state. See the register
summary in
Table 386. SCR bit assignments
The CCR is a read-only register and indicates some aspects of the behavior of the
Cortex-M0 processor. See the register summary in
The bit assignments are:
Bits
[2]
[1]
[0]
Bits
[31:5]
[4]
[3]
[2]
[1]
[0]
Name
-
SEVONPEND
-
SLEEPDEEP
SLEEPONEXIT Indicates sleep-on-exit when returning from Handler mode to Thread
-
SYSRESETREQ
VECTCLRACTIVE
-
Name
Table 25–382
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 15 February 2011
for its attributes. The bit assignments are:
Function
Reserved.
Send Event on Pending bit:
0 = only enabled interrupts or events can wakeup the processor,
disabled interrupts are excluded
1 = enabled events and all interrupts, including disabled interrupts,
can wakeup the processor.
When an event or interrupt enters pending state, the event signal
wakes up the processor from WFE. If the processor is not waiting for
an event, the event is registered and affects the next WFE.
The processor also wakes up on execution of an SEV instruction.
Reserved.
Controls whether the processor uses sleep or deep sleep as its low
power mode:
0 = sleep
1 = deep sleep.
mode:
0 = do not sleep when returning to Thread mode.
1 = enter sleep, or deep sleep, on return from an ISR to Thread
mode.
Setting this bit to 1 enables an interrupt driven application to avoid
returning to an empty main application.
Reserved.
Type
WO
WO
-
Chapter 25: LPC122x Appendix ARM Cortex-M0
Function
System reset request:
0 = no effect
1 = requests a system level reset.
This bit reads as 0.
Reserved for debug use. This bit reads as 0. When
writing to the register you must write 0 to this bit,
otherwise behavior is Unpredictable.
Reserved.
Table 25–382
for the CCR attributes.
UM10441
© NXP B.V. 2011. All rights reserved.
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