OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 325

• Manufacturer Part Number: OM13013,598
• Description: BOARD DEMO IAR LPC1227 JLINKLITE
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of OM13013,598

• Design Resources: LPC122x-SK Brd Schematic
• Processor To Be Evaluated: LPC1227
• Processor Series: LPC122x
• Data Bus Width: 32 bit
• Interface Type: UART, SSP, SPI, I2C
• Cpu Core: ARM Cortex-M0
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3 V to 3.6 V
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6885

21.1 How to read this chapter
21.2 Introduction
21.3 Features
21.4 Description
UM10441
User manual
The micro DMA controller is available on all LPC122x parts.
The micro DMA controller is a very low-gate-count DMA compatible with the AMBA
AHB-Lite protocol for DMA transfers. The micro DMA registers are programmed through
the APB interface.
The micro DMA controller contains an APB register interface, the AHB-Lite master
interface to the AHB multi-layer matrix, and the DMA control block (see
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UM10441
Chapter 21: LPC122x General purpose micro DMA controller
Rev. 1 — 15 February 2011
Single AHB-Lite master for transferring data using a 32-bit address bus and 32-bit
data bus.
21 DMA channels.
Dedicated handshake signals and programmable priority level for each channel.
Each priority level arbitrates using a fixed priority that is determined by the DMA
channel number.
Supports memory-to-memory, memory-to-peripheral, and peripheral-to-memory
transfers.
Supports multiple DMA cycle types and multiple DMA transfer widths.
Each DMA channel can access a primary and an alternate channel control data
structure.
The channel control data is stored in system memory in little-endian format.
Performs all DMA transfers using single AHB-Lite transfers. Burst transfers are not
supported.
The destination data width is equal to the source data width.
The number of transfers in a single DMA cycle can be programmed from 1 to 1024.
The transfer address increment can be greater than the data width.
Single output to indicate when an error condition occurs on the AHB.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 15 February 2011
© NXP B.V. 2011. All rights reserved.
Figure
User manual
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