OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 334

• Manufacturer Part Number: OM13013,598
• Description: BOARD DEMO IAR LPC1227 JLINKLITE
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of OM13013,598

• Design Resources: LPC122x-SK Brd Schematic
• Processor To Be Evaluated: LPC1227
• Processor Series: LPC122x
• Data Bus Width: 32 bit
• Interface Type: UART, SSP, SPI, I2C
• Cpu Core: ARM Cortex-M0
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3 V to 3.6 V
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6885

NXP Semiconductors
UM10441
User manual
21.6.13 Channel primary-alternate set register
Table 332. Channel enable clear register (CHNL_ENABLE_CLR, address 0x4004 C02C) bit
This register is a read/write register and configures a DMA channel c (c = 0 to 20) to use
the alternate data structure. Reading the register returns the status of which data structure
is in use for the corresponding DMA channel. Writing to a bit where a DMA channel is not
implemented has no effect.
Remark: The controller toggles the value of the CHNL_PRI_ALT_SET[c] bit after it
completes one of the following:
Table 333. Channel primary-alternate set register (CHNL_PRI_ALT_SET, address 0x4004
Bit
20:0
31:21
Bit
20:0
31:21 -
•
•
•
the four transfers that the primary data structure specifies for a memory scatter-gather
or peripheral scatter-gather DMA cycle. For details, see the ARM micro DMA
documentation.
all the transfers that the primary data structure specifies for a ping-pong DMA cycle.
all the transfers that the alternate data structure specifies for the following DMA cycle
types:
– ping-pong.
– memory scatter-gather. For details, see the ARM micro DMA (PL230)
– peripheral scatter-gather. For details, see the ARM micro DMA (PL230)
Symbol
CHNL_PRI_ALT_
SET
documentation.
documentation.
Symbol
CHNL_ENABLE_
CLR
-
description
C030) bit description
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 15 February 2011
Description
Returns the channel control data structure status, or selects the
alternate data structure for the corresponding DMA channel c.
Read as:
Bit [c] = 0: DMA channel c is using the primary data structure.
Bit [c] = 1: DMA channel c is using the alternate data structure.
Write as:
Bit [c] = 0: No effect. Use the CHNL_PRI_ALT_CLR Register to
set bit [c] to 0.
Bit [c] = 1: Selects the alternate data structure for channel c.
Reserved.
Chapter 21: LPC122x General purpose micro DMA controller
Description
Set the appropriate bit to disable the corresponding DMA
channel.
Write as:
Bit [c] = 0: No effect. Use the CHNL_ENABLE_SET
Register to enable DMA channels.
Bit [c] = 1 Disables channel c.
Reserved.
UM10441
© NXP B.V. 2011. All rights reserved.
334 of 442
Reset
value
-
-
Reset
value
0x0
-