OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 26

• Manufacturer Part Number: OM13013,598
• Description: BOARD DEMO IAR LPC1227 JLINKLITE
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of OM13013,598

• Design Resources: LPC122x-SK Brd Schematic
• Processor To Be Evaluated: LPC1227
• Processor Series: LPC122x
• Data Bus Width: 32 bit
• Interface Type: UART, SSP, SPI, I2C
• Cpu Core: ARM Cortex-M0
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3 V to 3.6 V
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6885

NXP Semiconductors
UM10441
User manual
4.5.20 CLKOUT clock source update enable register
4.5.21 CLKOUT clock divider register
4.5.22 POR captured PIO status register 0
Table 26.
This register updates the clock source of the CLKOUT pin with the new clock after the
CLKOUTCLKSEL register has been written to. In order for the update to take effect at the
input of the CLKOUT pin, first write a zero to the CLKCLKUEN register and then write a
one to CLKCLKUEN.
Table 27.
This register determines the divider value for the clkout_clk signal on the CLKOUT pin.
Table 28.
The PIOPORCAP0 register captures the state (HIGH or LOW) of the PIO pins of ports 0,1,
and 2 (pins PIO2_0 to PIO2_7) at power-on-reset. Each bit represents the reset state of
one GPIO pin. This register is a read-only status register.
Bit
1:0
31:2
Bit
0
31:1
Bit
7:0
31:8
Symbol
SEL
-
Symbol
ENA
-
Symbol
DIV
-
CLKOUT clock source select register (CLKOUTCLKSEL, address 0x4004 80E0) bit
description
CLKOUT clock source update enable register (CLKOUTUEN, address 0x4004
80E4) bit description
CLKOUT clock divider registers (CLKOUTDIV, address 0x4004 80E8) bit
description
All information provided in this document is subject to legal disclaimers.
Value
0x0
0x1
0x2
0x3
Description
Clock output divider values
0: Disable CLKOUT.
1: Divide by 1.
to
255: Divide by 255.
-
Reserved
Value
0
1
-
Rev. 1 — 15 February 2011
Description
CLKOUT clock source
IRC oscillator
System oscillator
Watchdog oscillator
Main clock
Reserved
Description
Enable CLKOUT clock source update
No change
Update clock source
Reserved
Chapter 4: LPC122x System control (SYSCON)
UM10441
© NXP B.V. 2011. All rights reserved.
Reset value
0
0x00
Reset value
0
0x00
26 of 442
Reset
value
00
0x00