OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 305
OM13013,598
Manufacturer Part Number
OM13013,598
Description
BOARD DEMO IAR LPC1227 JLINKLITE
Manufacturer
NXP Semiconductors
Series
-r
Specifications of OM13013,598
Design Resources
LPC122x-SK Brd Schematic
Processor To Be Evaluated
LPC1227
Processor Series
LPC122x
Data Bus Width
32 bit
Interface Type
UART, SSP, SPI, I2C
Cpu Core
ARM Cortex-M0
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Operating Supply Voltage
3 V to 3.6 V
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-6885
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UM10441
User manual
Fig 53. Boot process flowchart
(1) For details on handling the crystal frequency, see
20.5.3 Boot process flowchart
20.5.4 Criterion for Valid User Code
CRP3/NO_ISP
USER CODE
WATCHDOG
ENABLED?
FLAG SET?
ENABLED?
INITIALIZE
CRP1/2/3
yes
yes
yes
no
RESET
VALID?
A
Criterion for valid user code: The reserved Cortex-M0 exception vector location 7 (offset
0x 0000 001C in the vector table) should contain the 2’s complement of the check-sum of
table entries 0 through 6. This causes the checksum of the first 8 table entries to be 0. The
boot loader code checksums the first 8 locations in sector 0 of the flash. If the result is 0,
then execution control is transferred to the user code.
no
yes
no
no
RECEIVE CRYSTAL FREQUENCY
RUN ISP COMMAND HANDLER
no
(PIO0_12 = LOW)
RUN AUTO-BAUD
ENABLE DEBUG
SUCCESSFUL?
All information provided in this document is subject to legal disclaimers.
AUTO-BAUD
ENTER ISP
yes
yes
MODE?
no
Rev. 1 — 15 February 2011
Section 20.8.8 “Reinvoke ISP” on page 322
no
Chapter 20: LPC122x Flash ISP/IAP
USER CODE
no
VALID?
EXECUTE INTERNAL
USER CODE
yes
A
UM10441
© NXP B.V. 2011. All rights reserved.
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