OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 400

• Manufacturer Part Number: OM13013,598
• Description: BOARD DEMO IAR LPC1227 JLINKLITE
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of OM13013,598

• Design Resources: LPC122x-SK Brd Schematic
• Processor To Be Evaluated: LPC1227
• Processor Series: LPC122x
• Data Bus Width: 32 bit
• Interface Type: UART, SSP, SPI, I2C
• Cpu Core: ARM Cortex-M0
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3 V to 3.6 V
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6885

NXP Semiconductors
UM10441
User manual
25.4.5.9.1 Syntax
25.4.5.9.2 Operation
25.4.5.9.3 Restrictions
25.4.5.9.4 Condition flags
25.4.5.9.5 Examples
25.4.6.1.1 Syntax
25.4.6.1 B, BL, BX, and BLX
25.4.6 Branch and control instructions
TST Rn, Rm
where:
This instruction tests the value in a register against another register. It updates the
condition flags based on the result, but does not write the result to a register.
The TST instruction performs a bitwise AND operation on the value in Rn and the value in
Rm. This is the same as the ANDS instruction, except that it discards the result.
To test whether a bit of Rn is 0 or 1, use the TST instruction with a register that has that bit
set to 1 and all other bits cleared to 0.
In these instructions, Rn and Rm must only specify R0-R7.
This instruction:
Table 370
Table 370. Branch and control instructions
Branch instructions.
B{cond} label
BL label
Mnemonic
B{cc}
BL
BLX
BX
•
•
Rn is the register holding the first operand.
Rm the register to test against.
updates the N and Z flags according to the result
does not affect the C or V flags.
TST
shows the branch and control instructions:
R0, R1 ; Perform bitwise AND of R0 value and R1 value,
All information provided in this document is subject to legal disclaimers.
Brief description
Branch {conditionally}
Branch with Link
Branch indirect with Link
Branch indirect
Rev. 1 — 15 February 2011
; condition code flags are updated but result is discarded
Chapter 25: LPC122x Appendix ARM Cortex-M0
See
Section 25–25.4.6.1
Section 25–25.4.6.1
Section 25–25.4.6.1
Section 25–25.4.6.1
UM10441
© NXP B.V. 2011. All rights reserved.
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