OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 28
OM13013,598
Manufacturer Part Number
OM13013,598
Description
BOARD DEMO IAR LPC1227 JLINKLITE
Manufacturer
NXP Semiconductors
Series
-r
Specifications of OM13013,598
Design Resources
LPC122x-SK Brd Schematic
Processor To Be Evaluated
LPC1227
Processor Series
LPC122x
Data Bus Width
32 bit
Interface Type
UART, SSP, SPI, I2C
Cpu Core
ARM Cortex-M0
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Operating Supply Voltage
3 V to 3.6 V
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-6885
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UM10441
User manual
4.5.26 System tick counter calibration register
4.5.27 AHB matrix master priority register
Table 32.
This register determines the value of the SYST_CALIB register (see
Table 33.
The AHB matrix master priority register determines the priority with which the AHB
masters can access the bus.
Bit
1:0
3:2
4
31:5 -
Bit
25:0
31:26
Symbol
BODRSTLEV
BODINTVAL
BODRSTENA
Symbol
CAL
-
BOD control register (BODCTRL, address 0x4004 8150) bit description
System tick timer calibration register (SYSTCKCAL, address 0x4004 8154) bit
description
All information provided in this document is subject to legal disclaimers.
Value Description
0x0
0x1
0x2
0x3
0x0
0x1
0x2
0x3
0
1
-
Rev. 1 — 15 February 2011
Description
System tick timer calibration value
Reserved
BOD reset level
Reserved. Writing 00 to these bits will not change the BOD
reset level.
Level 1: The reset assertion threshold voltage is 2.038 V;
the reset de-assertion threshold voltage is 2.180 V.
Level 2: The reset assertion threshold voltage is 2.336 V;
the reset de-assertion threshold voltage is 2.471 V.
Level 3: The reset assertion threshold voltage is 2.624 V;
the reset de-assertion threshold voltage is 2.761 V.
BOD interrupt level
Reserved. Writing 00 to these bits will not change the
interrupt level.
Level 1:The interrupt assertion threshold voltage is
2.248 V; the interrupt de-assertion threshold voltage is
2.385 V.
Level 2: The interrupt assertion threshold voltage is
2.541 V; the interrupt de-assertion threshold voltage is
2.669 V.
Level 3: The interrupt assertion threshold voltage is
2.828 V; the interrupt de-assertion threshold voltage is
2.929 V.
BOD reset enable
Disable reset function.
Enable reset function.
Reserved
Chapter 4: LPC122x System control (SYSCON)
Table
UM10441
© NXP B.V. 2011. All rights reserved.
253).
Reset value
0x00
0x00
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