OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 327

• Manufacturer Part Number: OM13013,598
• Description: BOARD DEMO IAR LPC1227 JLINKLITE
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of OM13013,598

• Design Resources: LPC122x-SK Brd Schematic
• Processor To Be Evaluated: LPC1227
• Processor Series: LPC122x
• Data Bus Width: 32 bit
• Interface Type: UART, SSP, SPI, I2C
• Cpu Core: ARM Cortex-M0
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3 V to 3.6 V
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6885

NXP Semiconductors
21.5 Clocking and power control
UM10441
User manual
21.4.2 DMA system connections
The type of connection between the micro DMA and the supported peripheral devices
depends on the DMA functions implemented in those peripherals. SSP uses single
transfer and transfer requests, UART and ADC use transfer requests allowing one or
more transfers. See
DMA channel numbers used by the supported peripherals.
Table 319. DMA connections
[1]
The DMA interrupt is connected to the NVIC (see
generated by the DMA done signals for each channel and the DMA error condition, if
enabled. See also
The clock to the micro DMA controller is provided by the system clock, which is controlled
by the SYSAHBCLKDIV register
through the System AHB clock control register bit 12
Peripheral
UART0 Tx
UART0 Rx
UART1 Tx
UART1 Rx
SSP Tx
SSP Rx
ADC
RTC
32-bit Timer 0 match 0
32-bit Timer 0 match 1
32-bit Timer 1 match 0
32-bit Timer 1 match 1
16-bit Timer 0 match 0
16-bit Timer 1 match 0
Comparator 0
Comparator 1
PIO 0
PIO 1
PIO 2
reserved
reserved
Any DMA channel not used for peripheral DMA may be used to do a software triggered memory-to-memory
transfer.
All information provided in this document is subject to legal disclaimers.
Table
Table 341
Rev. 1 — 15 February 2011
Chapter 21: LPC122x General purpose micro DMA controller
341.
for more details on transfer types.
(Table
20). The micro DMA controller can be disabled
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
DMA channel single DMA
0
1
2
Table
(Table
4). The interrupt signals are
transfer request
-
-
-
-
yes
yes
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
21) for power savings.
Table 319
UM10441
© NXP B.V. 2011. All rights reserved.
DMA transfer
request
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
shows the
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