OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 356

• Manufacturer Part Number: OM13013,598
• Description: BOARD DEMO IAR LPC1227 JLINKLITE
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of OM13013,598

• Design Resources: LPC122x-SK Brd Schematic
• Processor To Be Evaluated: LPC1227
• Processor Series: LPC122x
• Data Bus Width: 32 bit
• Interface Type: UART, SSP, SPI, I2C
• Cpu Core: ARM Cortex-M0
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3 V to 3.6 V
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6885

25.1 Introduction
25.2 About the Cortex-M0 processor and core peripherals
UM10441
User manual
Fig 60. Cortex-M0 implementation
Interrupts
Cortex-M0 components
The following material is using the ARM Cortex-M0 User Guide. Minor changes have
been made regarding the specific implementation of the Cortex-M0 for the LPC122x.
The Cortex-M0 processor is an entry-level 32-bit ARM Cortex processor designed for a
broad range of embedded applications. It offers significant benefits to developers,
including:
The Cortex-M0 processor is built on a highly area and power optimized 32-bit processor
core, with a 3-stage pipeline von Neumann architecture. The processor delivers
exceptional energy efficiency through a small but powerful instruction set and extensively
optimized design, providing high-end processing hardware including a single-cycle
multiplier.
The Cortex-M0 processor implements the ARMv6-M architecture, which is based on the
16-bit Thumb instruction set and includes Thumb-2 technology. This provides the
exceptional performance expected of a modern 32-bit architecture, with a higher code
density than other 8-bit and 16-bit microcontrollers.
•
•
•
•
•
UM10441
Chapter 25: LPC122x Appendix ARM Cortex-M0
Rev. 1 — 15 February 2011
a simple architecture that is easy to learn and program
ultra-low power, energy efficient operation
excellent code density
deterministic, high-performance interrupt handling
upward compatibility with Cortex-M processor family.
Cortex-M0 processor
Controller
Vectored
Interrupt
All information provided in this document is subject to legal disclaimers.
Nested
(NVIC)
Rev. 1 — 15 February 2011
AHB-Lite interface to system
Cortex-M0
Bus matrix
processor
core
Breakpoint
watchpoint
Debugger
interface
Debug
and
unit
Serial Wire debug-port
Access Port
Debug
(DAP)
© NXP B.V. 2011. All rights reserved.
User manual
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