OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 165
OM13013,598
Manufacturer Part Number
OM13013,598
Description
BOARD DEMO IAR LPC1227 JLINKLITE
Manufacturer
NXP Semiconductors
Series
-r
Specifications of OM13013,598
Design Resources
LPC122x-SK Brd Schematic
Processor To Be Evaluated
LPC1227
Processor Series
LPC122x
Data Bus Width
32 bit
Interface Type
UART, SSP, SPI, I2C
Cpu Core
ARM Cortex-M0
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Operating Supply Voltage
3 V to 3.6 V
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-6885
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UM10441
User manual
handler routine can determine the cause of the interrupt and how to clear the active
interrupt. The IIR must be read in order to clear the interrupt prior to exiting the Interrupt
Service Routine.
The UART RLS interrupt (IIR[3:1] = 011) is the highest priority interrupt and is set
whenever any one of four error conditions occur on the UART RX input: overrun error
(OE), parity error (PE), framing error (FE) and break interrupt (BI). The UART RX error
condition that set the interrupt can be observed via LSR[4:1]. The interrupt is cleared upon
an LSR read.
The UART RDA interrupt (IIR[3:1] = 010) shares the second level priority with the CTI
interrupt (IIR[3:1] = 110). The RDA is activated when the UART RX FIFO reaches the
trigger level defined in FCR7:6 and is reset when the UART RX FIFO depth falls below the
trigger level. When the RDA interrupt goes active, the CPU can read a block of data
defined by the trigger level.
The CTI interrupt (IIR[3:1] = 110) is a second level interrupt and is set when the UART RX
FIFO contains at least one character and no UART RX FIFO activity has occurred in 3.5 to
4.5 character times. Any UART RX FIFO activity (read or write of UART RSR) will clear
the interrupt. This interrupt is intended to flush the UART RBR after a message has been
received that is not a multiple of the trigger level size. For example, if a peripheral wished
to send a 105 character message and the trigger level was 10 characters, the CPU would
receive 10 RDA interrupts resulting in the transfer of 100 characters and 1 to 5 CTI
interrupts (depending on the service routine) resulting in the transfer of the remaining 5
characters.
Table 168. UART Interrupt Handling
[1]
[2]
IIR[3:0]
value
0001
0110
0100
1100
0010
Values "0000", “0011”, “0101”, “0111”, “1000”, “1001”, “1010”, “1011”,”1101”,”1110”,”1111” are reserved.
For details see
[1]
Priority Interrupt
-
Highest RX Line
Second RX Data
Second Character
Third
All information provided in this document is subject to legal disclaimers.
Section 10.5.8 “UART Line Status Register”
type
None
Status /
Error
Available
Time-out
indication
THRE
Rev. 1 — 15 February 2011
Interrupt source
None
OE
RX data available or trigger level reached in FIFO
(FCR0=1)
Minimum of one character in the RX FIFO and no
character input or removed during a time period
depending on how many characters are in FIFO
and what the trigger level is set at (3.5 to 4.5
character times).
The exact time will be:
[(word length) × 7 - 2] × 8 + [(trigger level - number
of characters) × 8 + 1] RCLKs
THRE
[2]
or PE
[2]
[2]
or FE
[2]
or BI
[2]
Chapter 10: LPC122x UART1
UM10441
© NXP B.V. 2011. All rights reserved.
Interrupt
reset
-
LSR Read
RBR
Read
UART FIFO
drops below
trigger level
RBR
Read
IIR Read
(if source of
interrupt) or
THR write
165 of 442
[3]
[3]
or
[4]
[2]
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