MCF5272VF66 Freescale, MCF5272VF66 Datasheet - Page 99

• Manufacturer Part Number: MCF5272VF66
• Manufacturer: Freescale

Specifications of MCF5272VF66

• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Not Compliant

Chapter 3
Hardware Multiply/Accumulate (MAC) Unit
This chapter describes the MCF5272 multiply/accumulate (MAC) unit, which executes integer multiply,
multiply-accumulate, and miscellaneous register instructions. The MAC is integrated into the operand
execution pipeline (OEP).
3.1
The MAC unit provides hardware support for a limited set of digital signal processing (DSP) operations
used in embedded code, while supporting the integer multiply instructions in the ColdFire microprocessor
family.
The MAC unit provides signal processing capabilities for the MCF5272 in a variety of applications
including digital audio and servo control. Integrated as an execution unit in the processor’s OEP, the MAC
unit implements a three-stage arithmetic pipeline optimized for 16 x 16 multiplies. Both 16- and 32-bit
input operands are supported by this design in addition to a full set of extensions for signed and unsigned
integers plus signed, fixed-point fractional input operands.
The MAC unit provides functionality in three related areas:
Each of the three areas of support is addressed in detail in the succeeding sections. Logic that supports this
functionality is contained in a MAC module, as shown in
Freescale Semiconductor
•
•
•
Signed and unsigned integer multiplies
Multiply-accumulate operations supporting signed, unsigned, and signed fractional operands
Miscellaneous register operations
Overview
MCF5272 ColdFire
Figure 3-1. ColdFire MAC Multiplication and Accumulation
®
Operand Y
Integrated Microprocessor User’s Manual, Rev. 3
Accumulator
Shift 0,1,-1
+/-
X
Operand X
Figure
3-1.
3-1