MCF5272VF66 Freescale, MCF5272VF66 Datasheet - Page 350

• Manufacturer Part Number: MCF5272VF66
• Manufacturer: Freescale

Specifications of MCF5272VF66

• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Not Compliant

Queued Serial Peripheral Interface (QSPI) Module
14.5.3
Table 14-5
14-12
Address
Reset
11–8
Field
R/W
Bits
7–4
3–0
15
14
13
12
HALT WREN WRTO CSIV
gives QWR field descriptions.
15
NEWQP
ENDQP
CPTQP
QSPI Wrap Register (QWR)
WREN
WRTO
Name
HALT
CSIV
14
QSPI_CS inactive level.
Halt transfers. Assertion of this bit causes the QSPI to stop execution of commands once it has
completed execution of the current command.
Wraparound enable. Enables wraparound mode.
0 Execution stops after executing the command pointed to by QWR[ENDQP].
1 After executing command pointed to by QWR[ENDQP], wrap back to entry zero, or the entry pointed
Wraparound location. Determines where the QSPI wraps to in wraparound mode.
0 Wrap to RAM entry zero.
1 Wrap to RAM entry pointed to by QWR[NEWQP].
0 QSPI chip select outputs return to zero when not driven from the value in the current command RAM
1 QSPI chip select outputs return to one when not driven from the value in the current command RAM
End of queue pointer. Points to the RAM entry that contains the last transfer description in the queue.
Completed queue entry pointer. Points to the RAM entry that contains the last command to have been
completed. This field is read only.
Start of queue pointer. This 4-bit field points to the first entry in the RAM to be executed on initiating a
transfer.
MCF5272 ColdFire
to by QWR[NEWQP] and continue execution.
entry during a transfer (that is, inactive state is 0, chip selects are active high).
entry during a transfer (that is, inactive state is 1, chip selects are active low).
13
12
Figure 14-7. QSPI Wrap Register (QWR)
Table 14-5. QWR Field Descriptions
11
®
Integrated Microprocessor User’s Manual, Rev. 3
ENDQP
0000_0000_0000_0000
MBAR + 0x00A8
R/W
8
Description
7
–
4
Freescale Semiconductor
3
NEWQP
0