MCF5272VF66 Freescale, MCF5272VF66 Datasheet - Page 155

• Manufacturer Part Number: MCF5272VF66
• Manufacturer: Freescale

Specifications of MCF5272VF66

• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Not Compliant

Freescale Semiconductor
Instruction
bcc.{b,w}
bra.{b,w}
bsr.{b,w}
addq.l
divs.w
divu.w
addx.l
cmpi.l
link.w
addi.l
andi.l
cmp.l
divu.l
extb.l
divs.l
ext.w
add.l
add.l
and.l
and.l
bchg
bchg
eori.l
clr.w
asr.l
bset
bset
clr.b
eor.l
ext.l
asl.l
bclr
bclr
btst
btst
jmp
clr.l
lea
jsr
Operand Syntax
{Dy,#imm},Dx
{Dy,#imm},Dx
#imm,<ea>x
#imm,<ea>x
#imm,<ea>x
#imm,<ea>x
#imm,<ea>x
Table 5-22. PST/DDATA Specification for User-Mode Instructions
<ea>y,Rx
Dy,<ea>x
<ea>y,Dx
Dy,<ea>x
Dy,<ea>x
Dy,<ea>x
Dy,<ea>x
Dy,<ea>x
<ea>y,Rx
<ea>y,Dx
<ea>y,Dx
<ea>y,Dx
<ea>y,Dx
Dy,<ea>x
<ea>y,Ax
#imm,Dx
#imm,Dx
#imm,Dx
#imm,Dx
Ay,#imm
MCF5272 ColdFire
<ea>x
<ea>x
<ea>x
<ea>x
<ea>x
Dy,Dx
Dx
Dx
Dx
PST = 0x1, {PST = 0xB, DD = source operand}
PST = 0x1, {PST = 0xB, DD = source}, {PST = 0xB, DD = destination}
PST = 0x1, {PST = 0xB, DD = source}, {PST = 0xB, DD = destination}
PST = 0x1, {PST = 0xB, DD = source operand}
PST = 0x1, {PST = 0xB, DD = source}, {PST = 0xB, DD = destination}
PST = 0x1
PST = 0x1
if taken, then PST = 0x5, else PST = 0x1
PST = 0x1, {PST = 0x8, DD = source}, {PST = 0x8, DD = destination}
PST = 0x1, {PST = 0x8, DD = source}, {PST = 0x8, DD = destination}
PST = 0x5
PST = 0x1, {PST = 0x8, DD = source}, {PST = 0x8, DD = destination}
PST = 0x5, {PST = 0xB, DD = destination operand}
PST = 0x1, {PST = 0x8, DD = source operand}
PST = 0x1, {PST = 0x8, DD = source operand}
PST = 0x1, {PST = 0x8, DD = destination operand}
PST = 0x1, {PST = 0xB, DD = destination operand}
PST = 0x1, {PST = 0x9, DD = destination operand}
PST = 0x1, {PST = 0xB, DD = source operand}
PST = 0x1
PST = 0x1, {PST = 0xB, DD = source operand}
PST = 0x1, {PST = 0x9, DD = source operand}
PST = 0x1
PST = 0x1
PST = 0x1
PST = 0x1
PST = 0x5, {PST = [0x9AB], DD = target address}
PST = 0x5, {PST = [0x9AB], DD = target address},
PST = 0x1
PST = 0x1, {PST = 0xB, DD = destination operand}
PST = 0x1
PST = 0x1
PST = 0x1
PST = 0x1, {PST = 0x8, DD = source}, {PST = 0x8, DD = destination}
PST = 0x1, {PST = 0x8, DD = source}, {PST = 0x8, DD = destination}
PST = 0x1, {PST = 0x8, DD = source}, {PST = 0x8, DD = destination}
PST = 0x1, {PST = 0xB, DD = source operand}
PST = 0x1, {PST = 0x9, DD = source operand}
PST = 0x1, {PST = 0xB, DD = source}, {PST = 0xB, DD = destination}
{PST = 0xB , DD = destination operand}
®
Integrated Microprocessor User’s Manual, Rev. 3
PST/DDATA
1
1
Debug Support
5-37