MCF5272VF66 Freescale, MCF5272VF66 Datasheet - Page 442

• Manufacturer Part Number: MCF5272VF66
• Manufacturer: Freescale

Specifications of MCF5272VF66

• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Not Compliant

Signal Descriptions
19.16.1.5 UART1 CTS (URT1_CTS/QSPI_CS2)
UART1: URT1_CTS is the clear-to-send input indicating to the UART1 module that it can begin data
transmission.
QSPI mode: This output pin provides a QSPI peripheral chip select, QSPI_CS2, when in Master mode.
QSPI_CS2 can be programmed to be active high or low.
19.16.1.6 UART1 RTS (URT1_RTS/INT5)
Interrupt mode: This pin can be used as INT5.
UART1: The URT1_RTS output is an automatic request to send output from the UART1 module. It can
be configured to be asserted and negated as a function of the RxFIFO level.
19.16.1.7 Serial Data Output (DOUT0/URT1_TxD)
IDL mode: The DOUT0 output is for clocking data out of IDL port 0. Data is clocked out of DOUT0 on
the rising edge of DCL0.
GCI mode: The DOUT0 output is for clocking data out of GCI port 0. DCL0 is twice the bit rate (two
clocks per data bit).
UART1: URT1_TxD is the transmitter serial data output for the UART1 module. The output is held high
('mark' condition) when the transmitter is disabled, idle, or operating in the local loop back mode. Data is
shifted out, least significant bit first, on this pin at the falling edge of the serial clock source.
19.16.1.8 D-Channel Request(DREQ0/PA10)
IDL mode: This pin can be independently configured as the DREQ0 output for signaling to a layer-1 S/T
transceiver that a frame of data is ready to be sent on the port 0 D channel.
Port A mode: In GCI or IDL modes this pin can be independently configured as PA10.
19.16.1.9 QSPI Chip Select 1 (QSPI_CS1/PA11)
QSPI mode: QSPI_CS1 is a QSPI peripheral chip select.
Port A mode: In GCI or IDL modes this pin can be independently configured as PA11.
19.16.2 GCI/IDL TDM Port 1
Physical Layer Interface port 1 is an additional GCI/IDL port. Also internally connected to these pins are
GCI/IDL serial ports 2 and 3.
19.16.2.1 GCI/IDL Data Clock (DCL1/GDCL1_OUT)
IDL mode: DCL1 is the data clock used to clock data in and out of the DIN1 and DOUT1 pins for IDL
port 1. Data is clocked in to DIN1 on the falling edge of DCL1. Data is clocked out of DOUT1 on the rising
edge of DCL1.
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MCF5272 ColdFire
Integrated Microprocessor User’s Manual, Rev. 3
19-32
Freescale Semiconductor