MCF5272VF66 Freescale, MCF5272VF66 Datasheet - Page 440
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MCF5272VF66
Manufacturer Part Number
MCF5272VF66
Description
Manufacturer
Freescale
Datasheet
1.MCF5272VF66.pdf
(544 pages)
Specifications of MCF5272VF66
Family Name
MCF5xxx
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
66MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
3.3V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
196
Package Type
MA-BGA
Lead Free Status / RoHS Status
Not Compliant
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Signal Descriptions
19.15.1 QSPI Synchronous Serial Data Output (QSPI_Dout/WSEL)
The QSPI synchronous serial data output (QSPI_Dout) can be programmed to be driven on the rising or
falling edge of SCK. Each byte is sent msb first.
WSEL configuration input is sampled on the rising edge of Reset Output (RSTO).
19.15.2 QSPI Synchronous Serial Data Input (QSPI_Din)
The QSPI synchronous serial data input (QSPI_Din) can be programmed to be sampled on the rising or
falling edge of QSPI_CLK. Each byte is written to RAM lsb first.
19.15.3 QSPI Serial Clock (QSPI_CLK/BUSW1)
The QSPI serial clock (QSPI_CLK/BUSW1) provides the serial clock from the QSPI. The polarity and
phase of QSPI_CLK are programmable. The output frequency is programmed according to the following
formula, in which n can be any value between 1 and 255:
At reset, QSPI_CLK/BUSW1 is used to configure the width of memory connected to CS0.
BUSW1 configuration input is sampled on the rising edge of Reset Output (RSTO).
19.15.4 Synchronous Peripheral Chip Select 0 (QSPI_CS0/BUSW0)
The synchronous peripheral chip select 0 (QSPI_CS0) output provides a QSPI peripheral chip select that
can be programmed to be active high or low. During reset, this pin is used to configure the width of
memory connected to CS0.
BUSW0 configuration input is sampled on the rising edge of Reset Output (RSTO).
19.15.5 Synchronous Peripheral Chip Select 1 (QSPI_CS1/PA11)
See
QSPI_CS1 can be programmed to be active high or low.
19.15.6 Synchronous Peripheral Chip Select 2 (QSPI_CS2/URT1_CTS)
See
19.15.7 Synchronous Peripheral Chip Select 3 (PA7/DOUT3/QSPI_CS3)
See
description for GPIO ports.
19-30
Section 19.16.1.9, “QSPI Chip Select 1
Section 19.16.1.5, “UART1 CTS
Section 19.16.3.3, “QSPI_CS3, Port 3 GCI/IDL Data Out 3, PA7
QSPI_CLK = CLKIN/(2 × n)
MCF5272 ColdFire
(URT1_CTS/QSPI_CS2).”
®
Integrated Microprocessor User’s Manual, Rev. 3
(QSPI_CS1/PA11).”
(PA7/DOUT3/QSPI_CS3).” See
Freescale Semiconductor
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