MCF5272VF66 Freescale, MCF5272VF66 Datasheet - Page 5

• Manufacturer Part Number: MCF5272VF66
• Manufacturer: Freescale

Specifications of MCF5272VF66

• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Not Compliant

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Freescale Semiconductor
MCF5272 Block Diagram ........................................................................................................ 1-2
ColdFire Pipeline..................................................................................................................... 2-2
ColdFire Multiply-Accumulate Functionality Diagram.............................................................. 2-3
ColdFire Programming Model ................................................................................................. 2-5
Condition Code Register (CCR).............................................................................................. 2-6
Status Register (SR) ............................................................................................................... 2-8
Vector Base Register (VBR) ................................................................................................... 2-8
Organization of Integer Data Formats in Data Registers ...................................................... 2-10
Organization of Integer Data Formats in Address Registers................................................. 2-10
Memory Operand Addressing ............................................................................................... 2-11
Exception Stack Frame Form................................................................................................ 2-27
ColdFire MAC Multiplication and Accumulation ...................................................................... 3-1
MAC Programming Model....................................................................................................... 3-2
SRAM Base Address Register (RAMBAR) ............................................................................. 4-3
Instruction Cache Block Diagram............................................................................................ 4-8
Cache Control Register (CACR) ........................................................................................... 4-12
Access Control Register Format (ACRn) .............................................................................. 4-14
Processor/Debug Module Interface......................................................................................... 5-1
PSTCLK Timing ...................................................................................................................... 5-2
Example JMP Instruction Output on PST/DDATA .................................................................. 5-5
Debug Programming Model .................................................................................................... 5-6
Address Attribute Trigger Register (AATR)............................................................................. 5-7
Address Breakpoint Registers (ABLR, ABHR)........................................................................ 5-9
Configuration/Status Register (CSR) .................................................................................... 5-10
Data Breakpoint/Mask Registers (DBR and DBMR) ............................................................. 5-12
Program Counter Breakpoint Register (PBR) ....................................................................... 5-13
Program Counter Breakpoint Mask Register (PBMR)........................................................... 5-13
Trigger Definition Register (TDR).......................................................................................... 5-14
BDM Serial Interface Timing ................................................................................................. 5-17
Receive BDM Packet ............................................................................................................ 5-18
Transmit BDM Packet ........................................................................................................... 5-18
BDM Command Format ........................................................................................................ 5-20
Command Sequence Diagram.............................................................................................. 5-21
RAREG
RAREG
WAREG
WAREG
READ
READ
ROM Base Address Register (ROMBAR).............................................................................. 4-5
Command/Result Formats ........................................................................................... 5-24
Command Sequence ................................................................................................... 5-24
/
/
/
/
RDREG
RDREG
WDREG
WDREG
MCF5272 ColdFire
Command Format .......................................................................................... 5-22
Command Sequence...................................................................................... 5-22
Command Format ......................................................................................... 5-23
Command Sequence .................................................................................... 5-23
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List of Figures
Integrated Microprocessor User’s Manual, Rev. 3
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