MCF5272VF66 Freescale, MCF5272VF66 Datasheet - Page 449

• Manufacturer Part Number: MCF5272VF66
• Manufacturer: Freescale

Specifications of MCF5272VF66

• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Not Compliant

Chapter 20
Bus Operation
The MCF5272 bus interface supports synchronous data transfers that can be terminated synchronously or
asynchronously and also can be burst or burst-inhibited between the MCF5272 and other devices in the
system. This chapter describes the functioning of the bus for data-transfer operations, error conditions, bus
arbitration, and reset operations. It includes detailed timing diagrams showing signal interaction. Refer
also to
Operation of the bus is defined for transfers initiated by the MCF5272 as a bus master. The MCF5272 does
not support external bus masters. The MCF5272 has three on-chip bus masters—the CPU, the Ethernet
controller, and the memory-to-memory DMA controller.
20.1
The following list summarizes the key bus operation features:
20.2
Table 20-1
Freescale Semiconductor
•
•
•
•
•
•
Figure 19-1
23 bits of address and 32 bits of data
Device physical data bus width configurable for 16 or 32 bits
Accesses 8-, 16-, and 32-bit port sizes
Generates byte, word, longword, and line size transfers
Burst and burst-inhibited transfer support
Internal termination generation
Features
Bus and Control Signals
summarizes MCF5272 bus signals described in
for an overview of how the signals interact with each module of the MCF5272.
MCF5272 ColdFire
Signal Name
INT[6:1]
CS[7:0]
BS[3:0]
D[31:0]
A[22:0]
Table 20-1. ColdFire Bus Signal Summary
R/W
TEA
OE
TA
®
Integrated Microprocessor User’s Manual, Rev. 3
Address bus
Byte strobes
Chip selects
Data bus
Interrupt request
Output enable
Read/write
Transfer acknowledge
Transfer error acknowledge
Description
Chapter 19, “Signal Descriptions.”
I/O
I/O
O
O
O
O
O
I
I
I
20-1